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audio codec for recordable dvd ADAV801 rev. 0 in fo rmation furn is h e d by an al o g dev i ces is believed to be a ccu rate and r e liable. how e ver, no r e spons i bili ty is assumed by analog devices fo r its use, nor f o r an y i n fri n geme nt s of p a t e nt s or ot her ri g h t s o f th ird parties th at may result fro m its use . specifications subject to chan g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot he rwi s e un der a n y p a t e nt or p a t e nt r i ghts of anal og de vices. trad emarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features stereo analog-to-digital converter (a dc) supports 48/96 kh z sample r a tes 102 db dynami c range single-ended i n put automatic le ve l control stereo digital-t o -analog converter (d ac) supports 32/44.1/48/96/192 khz s a mple rat e s 101 db dynami c range single-ended output asynchronous operation of adc and d a c stereo sample rate converter (src) input/output range: 8 k hz to 192 k hz 140 db dynami c range digital interf aces record playback auxiliar y record auxiliary playback s/pdif (iec609 58) input and o u tput digital interf ace receiver (dir) digital interf ace transmitter ( d it) pll-based audio mclk generators generates r e q u ired dvdr sys t em mclks device control via spi?-compatible serial port 64-lea d lqfp package function al block di ag ram analog-to-digital converter reference src digital-to-analog converter ADAV801 dit aux data output record data output control registers pll digital input/output switching matrix (datapath) playback data input aux data input dir vinl vinr vref filtd iauxl rcl k iauxbcl k iauxsdat a dirin olrclk obclk osdata oauxlrclk oauxbclk oauxsdata ditout co ut cin ccl k cl at ch syscl k 3 syscl k 2 syscl k 1 zerol/int zeror mcl k i xout xin mcl k o voutl voutr 04577-0-001 il rcl k ibcl k isdat a fi g u r e 1 . applic ati o ns dvd-r e co rdable all formats cd-r/w product overview the ad a v 801 is a s t er eo a u dio co dec in t e n d ed f o r a p p l ica t ion s su ch a s d v d or c d re c o rd e r s t h a t re qu i r e h i g h p e r f or m a nc e a nd f l ex i b le, co st-ef f e c t i ve pl a y b a ck an d r e co rd f u n c t i o n a l i t y . the ad a v 801 fea t ur es analog de vices p r o p r i eta r y , hig h p e r f o r ma n c e con v er t e r co r e s t o p r o v ide r e co r d ( a d c ), pl a y b a ck (d a c ), a nd f o r m a t co n v er sio n (s r c ) o n a sin g le c h i p . th e ad a v 801 r e co rd c h a n ne l f e a t ur es va r i a b le in p u t ga in t o al lo w f o r ad j u s t m e n t o f r e co r d e d in p u t le v e l s and a u to ma tic le ve l co n t r o l , fol l o w e d b y a hig h p e r f o r ma n c e st er e o ad c w h os e d i g i t a l output i s s e n t to t h e re c o rd i n t e r f a c e. t h e re c o rd ch an n e l als o f e a t ur es le ve l det e c t o r s tha t ca n be us e d in f e e d b a c k lo o p s to a d j u st i n put l e vel s f o r opt i m u m re c o rd i n g . t h e p l a y b a c k cha n n e l fe a t ur e s a hig h p e r f o r ma nce s t er e o d a c w i t h indep e n d en t di g i t a l vol u m e con t r o l. the s a m p le ra te co n v er t e r (s r c ) p r o v ides hig h p e r f o r ma n c e s a m p l e r a te c o n v e r s i on to a l l o w i n put s a n d output s t h a t re qu i r e dif f er en t s a m p le ra t e s t o b e ma tch e d . th e sr c i n p u t ca n b e s e l e c t e d f r om pl a y b a ck , a u x i l i ar y , di r , or a d c ( r e c ord ) . t h e s r c o u t p u t ca n be a p p l i e d t o t h e p l a y ba ck d a c, bo th m a i n a n d a u x i l i ar y re c o rd ch an nel s , a n d a di t . o p era t ion o f the ad a v 801 is c o n t r o l l ed via a n s p i-com p a t i b le s e r i a l in t e r f ace , w h ich a l lo ws t h e p r og ra mmin g o f in d i vi d u a l co n t r o l r e g i s t er s e t t in gs. th e ad a v 801 o p er a t es f r o m a sin g le ana l o g 3 . 3 v p o we r su p p ly and a dig i t a l p o we r su p p ly of 3 . 3 v wi t h o p tio n al dig i tal in t e r f ace r a n g e o f 3.0 v t o 3.6 v . the p a r t is h o us ed in a 64-lead l q fp p a c k a g e and is c h a r ac t e r - ize d fo r o p era t i o n o v er t h e commer c ial tem p era t ur e ra n g e o f ?40c t o +85c.
ADAV801 rev. 0 | page 2 of 56 table of contents specifications ..................................................................................... 3 test conditions ............................................................................. 3 ADAV801 specifications ............................................................. 3 timing specifications .................................................................. 6 temperature range ...................................................................... 7 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 11 functional description .................................................................. 15 adc section ............................................................................... 15 dac section ................................................................................ 18 sample rate converter (src) functional overview ............ 19 pll section ................................................................................. 22 spdif transmitter and receiver .............................................. 23 serial data ports ......................................................................... 27 interface control ............................................................................ 30 spi interface ................................................................................ 30 block reads and writes ............................................................. 30 layout considerations ................................................................... 54 adc ............................................................................................. 54 dac .............................................................................................. 54 pll ............................................................................................... 54 reset and power-down considerations ................................. 54 outline dimensions ....................................................................... 55 ordering guide .......................................................................... 55 revision history 7/04revision 0: initial version
ADAV801 rev. 0 | page 3 of 56 specifications test conditions test conditions, unless otherwise noted. table 1. test parameter condition supply voltage analog 3.3 v digital 3.3 v ambient temperature 25c master clock (xin) 12.288 mhz measurement bandwidth 20 hz to 20 khz word width (all converters) 24 bits load capacitance on digital outputs 100 pf adc input frequency 1007.8125 hz at ?1 dbfs dac output frequency 960.9673 hz at 0 dbfs digital input slave mode, i 2 s justified format digital output slave mode, i 2 s justified format ADAV801 specifications table 2. parameter min typ max unit comments pga section input impedance 4 k? minimum gain 0 db maximum gain 24 db gain step 0.5 db reference section absolute voltage, v ref 1.5 v v ref temperature coefficient 80 ppm/c adc section number of channels 2 resolution 24 bits dynamic range ?60 db input unweighted 99 db f s = 48 khz 98 db f s = 96 khz a-weighted 98 102 db f s = 48 khz 101 db f s = 96 khz total harmonic distortion plus noise input = ?1.0 dbfs ?88 db f s = 48 khz ?87 db f s = 96 khz analog input input range ( full scale) 1.0 v rms dc accuracy gain error ?1.5 ?0.8 db interchannel gain mismatch 0.05 db gain drift 1 mdb/c offset ?10 mv crosstalk (eiaj method) ?110 db volume control step size (256 steps) 0.39 % per step
ADAV801 rev. 0 | page 4 of 56 parameter min typ max unit comments maximum volume attenuation ?48 db mute attenuation db adc outputs all zero codes group delay f s = 48 khz 910 s f s = 96 khz 460 s adc low-pass digital decimation filter characteristics 1 pass-band frequency 22 khz sample rate: 48 khz 44 khz sample rate: 96 khz stop-band frequency 26 khz sample rate: 48 khz 52 khz sample rate: 96 khz stop-band attenuation 120 db sample rate: 48 khz 120 db sample rate: 96 khz pass-band ripple 0.01 db sample rate: 48 khz 0.01 db sample rate: 96 khz adc high-pass digital filter characteristics cutoff frequency 0.9 hz f s = 48 khz src section resolution 24 bits sample rate 8 192 khz xin = 27 mhz src mclk 138 f s-max 33 mhz f s-max is the greater of the input or output sample rate maximum sample rate ratios upsampling 1:8 downsampling 7.75:1 dynamic range 140 20 hz to f s /2, 1 khz, ?60 dbfs input, f in = 44.1 khz, f out = 48 khz total harmonic distortion plus noise 120 db 20 hz to f s /2, 1 khz, 0 dbfs input, f in = 44.1 khz, f out = 48 khz dac section number of channels 2 resolution 24 bits dynamic range 20 hz to 20 khz, ?60 db input unweighted 99 db f s = 48 khz 98 db f s = 96 khz a-weighted 97 101 db f s = 48 khz 100 db f s = 96 khz total harmonic distorton plus noise referenced to 1 v rms ?91 db f s = 48 khz ?90 db f s = 96 khz analog outputs output range ( full scale) 1.0 v rms output resistance 60 ? common-mode output voltage 1.5 v dc accuracy gain error ?2 ?0.8 db interchannel gain mismatch 0.05 db gain drift 1 mdb/c dc offset ?30 +30 mv crosstalk (eiaj method) ?110 db phase deviation 0.05 degrees mute attenuation ?95.625 db
ADAV801 rev. 0 | page 5 of 56 parameter min typ max unit comments volume control step size (256 steps) 0.375 db group delay 48 khz 630 s 96 khz 155 s 192 khz 66 s dac low-pass digital interpolation filter characteristics pass-band frequency 20 khz sample rate: 44.1 khz 22 khz sample rate: 48 khz 42 khz sample rate: 96 khz stop-band frequency 24 khz sample rate: 44.1 khz 26 khz sample rate: 48 khz 60 khz sample rate: 96 khz stop-band attenuation 70 db sample rate: 44.1 khz 70 db sample rate: 48 khz 70 db sample rate: 96 khz pass-band ripple 0.002 db sample rate: 44.1 khz 0.002 db sample rate: 48 khz 0.005 db sample rate: 96 khz pll section master clock input frequency 27/54 mhz generated system clocks mclko 27/54 mhz sysclk1 256 768 f s 256/384/512/768 32/44.1/ 48 khz sysclk2 256 768 f s 256/384/512/768 32/44.1/ 48 khz sysclk3 256 512 f s 256/512 32/44.1/48 khz jitter sysclk1 65 ps rms sysclk2 75 ps rms sysclk3 75 ps rms dir section input sample frequency 27.2 200 khz differential input voltage 200 mv dit section output sample frequency 27.2 200 khz digital i/o input voltage high, v ih 2.0 dvdd v input voltage low, v il 0.8 v input leakage, i ih @ v ih = 3.3 v 10 a input leakage, i il @ v il = 0 v 10 a output voltage high, v oh @ i oh = 0.4 ma 2.4 v output voltage low, v ol @ i ol = ?2 ma 0.4 v input capacitance 15 pf power supplies voltage, avdd 3.0 3.3 3.6 v voltage, dvdd 3.0 3.3 3.6 v voltage, odvdd 3.0 3.3 3.6 v
ADAV801 rev. 0 | page 6 of 56 parameter min typ max unit comments operating current all supplies at 3.3 v analog current 60 ma digital current 38 ma digital interface current 13 ma dirin/dirout current 5 ma pll current 18 ma power-down current reset low, no mclk analog current 18 ma digital current 2.5 ma digital interface current 700 a dirin/dirout current 3.5 ma pll current 900 a power supply rejection signal at analog supply pins ?70 db 1 khz, 300 mv p-p ?70 db 20 khz, 300 mv p-p 1 guaranteed by design. timing specifications timing specifications are guaranteed over the full temperature and supply range. table 3. parameter min typ max unit comments master clock and reset f mclk mclki frequency 12.288 54 mhz f xin xin frequency 27.0 54 mhz t reset reset low 20 ns spi port t cch cclk high 40 ns t ccl cclk low 40 ns t cis cin setup 10 ns to cclk rising edge t cih cin hold 10 ns from cclk rising edge t cls clatch setup 10 ns to cclk rising edge t clh clatch hold 10 ns from cclk rising edge t coe cout enable 15 ns from clatch falling edge t cod cout delay 20 ns from cclk falling edge t cots cout three-state 25 ns from clatch rising edge serial ports 1 slave mode t sbh xbclk high 40 ns t sbl xbclk low 40 ns f sbf xbclk frequency 64 f s t sls xlrclk setup 10 ns to xbclk rising edge t slh xlrclk hold 10 ns from xbclk rising edge t sds xsdata setup 10 ns to xbclk rising edge t sdh xsdata hold 10 ns from xbclk rising edge t sdd xsdata delay 10 ns from xbclk falling edge
ADAV801 rev. 0 | page 7 of 56 parameter min typ max unit comments master mode t mld xlrclk delay 5 ns from xbclk falling edge t mdd xsdata delay 10 ns from xbclk falling edge t mds xsdata setup 10 ns from xbclk rising edge t mdh xsdata hold 10 ns from xbclk rising edge 1 the prefix x refers to i-, o-, iau x-, or oaux- for the full pin name. temperature range table 4. min typ max unit specifications guaranteed 25 c functionality guaranteed ?40 +85 c storage ?65 +150 c
ADAV801 rev. 0 | page 8 of 5 6 absolute maximum ra tings table 5. p a r a m e t e r r a t i n g dvdd to dg nd and odvdd to dgnd 0 v to 4.6 v avdd to ag nd 0 v to 4.6 v digital inputs dgnd ? 0.3 v to dvdd + 0.3 v analog inputs agnd ? 0.3 v to avdd + 0.3 v agnd to dg nd ?0.3 v to +0.3 v reference voltage indefinite short circuit to ground soldering (10 s) 300c s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . esd c a ution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ADAV801 rev. 0 | page 9 of 5 6 pin conf igura t ion and fu nction descriptions nc vou t l nc vou t r oaux s data iaux lrclk iaux bclk iaux s data z erol/int zeror dvdd dgnd advdd adgnd pll_lf2 pll_lf1 pll_gnd pll_vdd dgnd sysclk1 sysclk2 sysclk3 xin xout 39 38 37 41 40 mclko mclki dvdd dgnd 36 35 34 33 42 43 44 45 46 47 48 17 1 8 19 20 21 22 2 3 24 ilrclk ibclk is data olrclk obclk os data dirin odvdd odgnd ditout oaux lrclk oaux bclk 1 2 3 4 5 6 7 8 9 10 11 12 6 4 63 6 2 61 60 5 9 58 cap ln cap lp agnd cap rp cap rn av dd agnd vr ef agnd filtd agnd av dd vinr vinl agnd avdd dir_lf dir_gnd dir_vdd reset clatch cin cclk cout 13 14 15 16 25 26 27 3 1 30 29 28 32 57 56 55 54 53 52 51 50 49 ADAV801 top view (not to scale) 04577-0-002 pin 1 indicator nc = no connect f i gure 2. pin config ur ation ta ble 6. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic i/o description 1 vinr i analog audio input, right channel. 2 vinl i analog audio input, left channel. 3 a g n d a n a l o g g r o u n d . 4 a v d d analog v o l t a g e s u p p l y . 5 dir_lf dir phase-locked loop (pll) fi lter pin. 6 dir_gnd supply ground f o r dir analog sectio n. this pin should be connected to agnd. 7 dir_vdd supply for dir a n alog section. this pin should be connected to avdd. 8 reset i asychronous reset input (active low). 9 clatch i chip select (control latch) pin of spi-compatible control interf ace. 10 cin i data input of sp i-co mpatible control interface. 11 cclk i clock input of s p i-compatible c o ntrol interface. 12 cout o data output of spi-co mpatible control interfac e. 1 3 z e r o l / i n t o left channel (output) zero flag or interrupt (output) flag. the func tion of this pin is determined by the intrpt p i n in dac control register 4. 14 zeror o right channel (output) zero fl ag. 15 dvdd digital voltage supply. 1 6 d g n d d i g i t a l g r o u n d . 1 7 i l r c l k i / o sampling cl ock (lrclk ) of playback digital input port. 18 ibclk i/o serial clo c k (bc l k) of playback digital input port. 19 isdata i data input of pl ayback digital i n put port. 2 0 o l r c l k i / o sampling cl ock (lrclk ) of record digital output port. 21 obclk i/o serial clo c k (bc l k) of record di gital output por t . 22 osdata o data output of record digital output port. 23 dirin i input to digital i n put receiver (s/ p dif). 24 odvdd interface digital voltage supply. 25 odgnd interface digital ground. 26 ditout o s/ pdif output f r om dit. 2 7 o a u x l r c l k i / o sampling cl ock (lrclk ) of aux i liary digital output port.
ADAV801 rev. 0 | page 10 of 56 pin no. mnemonic i/o description 28 oauxbclk i/o serial clock (bclk) of auxiliary digital output port. 29 oauxsdata o data output of auxiliary digital output port. 30 iauxlrclk i/o sampling clock (lrclk) of auxiliary digital input port. 31 iauxbclk i/o serial (bclk) of auxiliary digital input port. 32 iauxsdata i data input of auxiliary digital input port. 33 dgnd digital ground. 34 dvdd digital supply voltage. 35 mclki i external mclk input. 36 mclko o oscillator output. 37 xout i crystal input. 38 xin i crystal or external mclk input. 39 sysclk3 o system clock 3 (from pll2). 40 sysclk2 o system clock 2 (from pll2). 41 sysclk1 o system clock 1 (from pll1). 42 dgnd digital ground. 43 pll_vdd supply for pll analog section. th is pin should be connected to avdd. 44 pll_gnd ground for pll analog section. this pin should be connected to agnd. 45 pll_lf1 loop filter for pll1. 46 pll_lf2 loop filter for pll2. 47 adgnd analog ground (mixed signal). this pin should be connected to agnd. 48 advdd analog voltage supply (mixed signal). this pin should be connected to avdd. 49 voutr o right channel analog output. 50 nc no connect. 51 voutl o left channel analog output. 52 nc no connect. 53 avdd analog voltage supply. 54 agnd analog ground. 55 filtd output dac reference decoupling. 56 agnd analog ground. 57 vref voltage reference voltage. 58 agnd analog ground. 59 avdd analog voltage supply. 60 caprn adc modulator input filter capacitor (right channel, negative). 61 caprp adc modulator input filter capacitor (right channel, positive). 62 agnd analog ground. 63 caplp adc modulator input filter capacitor (left channel, positive). 64 capln adc modulator input filter capacitor (left channel, negative).
ADAV801 rev. 0 | page 11 of 56 typical perf orm ance cha r acte ristics frequency (normalized to f s ) magnitude (db) 0 ?5 0 ?100 ?150 0 0.5 1.0 1.5 2.0 04577-0-037 f i gure 3. adc comp osite f i lter respon se frequency (hz) magnitude (db) 5 ?5 0 ?15 ?10 ?25 ?20 ?30 0 5 10 15 20 04577-0-038 f i gur e 4 . adc h i gh-p a ss f i l t er resp o n se , f s = 4 8 kh z frequency (hz) magnitude (db) 5 ?5 0 ?15 ?10 ?25 ?20 ?30 0 5 10 15 20 04577-0-039 f i gur e 5 . adc h i gh-p a ss f i l t er resp o n se , f s = 9 6 kh z frequency (khz) magnitude (db) 0 ?50 ?100 ?150 0 9 6 192 288 384 04577-0-040 f i g u re 6. da c co m p os it e f i lt er r e s p on s e , 48 k h z frequency (khz) magnitude (db) 0 ?5 0 ?100 ?150 02 4 12 36 48 04577-0-041 f i gur e 7 . d a c p a ss -ba n d f i lt er resp o n se , 4 8 k h z frequency (khz) magnitude (db) 0.06 0.04 0.02 0.00 ? 0.06 ? 0.04 ? 0.02 0 8 16 24 04577-0-042 fi g u r e 8 . d a c fi l t e r r i p p l e , 4 8 k h z
ADAV801 rev. 0 | page 12 of 56 frequency (khz) magnitude (db) 0 ?5 0 ?100 ?150 0 192 384 576 768 04577-0-043 f i g u re 9. da c co m p os it e f i lt er r e s p on s e , 96 k h z frequency (khz) magnitude (db) 0 ?50 ? 100 ? 150 0 2 44 87 29 04577-0-044 6 f i g u re 10. da c p a s s -band f i l t er r e s p o n s e , 96 k h z frequency (khz) magnitude (db) 0.10 0.05 0.00 ?0.05 ?0.10 0 2 44 8 7 29 04577-0-045 6 f i g u re 11. da c f i l t e r r i p p l e , 96 k h z frequency (khz) mag n itude (db) 0 ?50 ? 100 ? 150 ? 200 0 384 768 1152 1536 04577-0-046 f i gu r e 12. d a c comp os it e f i lt er response , 192 khz frequency (khz) magnitude (db) 0 ?2 ?4 ?6 ?8 ?10 48 64 80 96 04577-0-047 f i g u re 2 k h z 13. da c p a s s -band f i l t er r e s p o n s e , 1 9 frequency (khz) magnitude (db) 0.50 0.40 0.30 0.20 0.10 0.00 ?0.10 ?0.30 ?0.40 ?0.20 ?0.50 0 8 16 32 64 04577-0-048 f i g u re 14. da c f i l r r i p p l e , 19 2 k h z t e
ADAV801 rev. 0 | page 13 of 56 frequency (khz) magnitude (db) 0 ?20 ?40 ?80 ? 100 ?60 ? 120 ? 140 ? 160 0 2 4 6 8 1 0 1 2 1 41 61 8 2 0 04577-0-049 dnr = 102db (a-weighted) f i g h z u re 15. da c d y n a m i c rang e , f s = 48 k frequency (khz) magnitude (db) 0 ?20 ?40 ?80 ? 100 ?60 ? 120 ? 140 ? 160 0246 8 1 0 1 2 1 4 1 6 1 8 2 0 04577-0-050 thd+n = 96db f i gure 16. d a c t h d + n, f s = 4 8 kh z frequency (khz) magnitude (db) 0 ?20 ?40 ?80 ? 100 ?60 ? 120 ? 140 ? 160 0 5 10 15 20 25 30 35 40 45 48 04577-0-051 dnr = 102db (a-weighted) f i g u re 17. da c d y n a m i c rang e , f s = 96 kh z frequency (khz) magnitude (db) 0 ?20 ?40 ?80 ? 100 ?60 ? 120 ? 140 ? 160 0 5 10 15 20 25 30 35 40 45 48 04577-0-052 thd+n = 95db f i gure 18. d a c t h d + n, f s = 9 6 kh z frequency (khz) magnitude (db) 0 ?20 ?40 ?80 ? 100 ?60 ? 120 ? 140 ? 160 0 5 10 15 20 04577-0-053 dnr = 102db (a-weighted) f i g u re 19. a d c d y n a m c rang e , f s = 48 kh z i frequency (khz) magnitude (db) 0 ?20 ?40 ?80 ? 100 ?60 ? 120 ? 140 ? 160 0 5 10 15 20 04577-0-054 thd+n = 92db (v in = ? 3db) f i gure 20. d a c t h d + n, f s = 4 8 kh z
ADAV801 rev. 0 | page 14 of 56 frequency (khz) ? 160 0 8 16 24 32 40 48 04577-0-055 magnitude (db) ?40 ? 8 0 ? 100 ?60 ? 120 ? 140 0 ?20 dnr = 102db (a-weighted) f i g u re 21. a d c d y n a m i c rang e , f s = 96 kh z frequency (khz) ? 160 0 8 16 24 32 40 48 magnitude (db) ?40 ?80 ? 100 ?60 0 ? 120 04577-0-056 ?20 ? 140 t h (v d + n = 9 2 d b in = ? 3db) f i gure 22. adc t h d + n, f s = 9 6 kh z
ADAV801 rev. 0 | page 15 of 56 t i o n c k c a n d b y a fa c t o r o f 8 a t h e s t h er t h e f u n c t i o n a l d e s c r i p adc sec t ion the a d a v 801 s ad c s e c t io n is im ple m e n t e d usin g a s e cond- o r der m u l t ib i t (5 b i ts) - ? mo du l a tor . t h e mo du l a tor i s s a m p le d a t ei t h er half o f th e ad c m c lk ra t e ( m o d u l a t o r c l o = 128 f s ) or o n e - qu ar te r of t h e a d c m c l k r a te ( m o d u l a t or c l o c k = 64 f s ) . t h e d i g i t a l d e c i m a tor c o ns i s t s of a si nc ^ 5 f i lte r fol l o w e d b y a cas c ade o f t h r e e half-b a n d fir f i l t ers. th e si n de cim a t e s b y a f a c t o r o f 16 a t 4 8 k h z 96 khz. e a ch o f t h e ha lf- b an d f i l t ers de cim a t e s b y a fac t o r o f 2. f i gur e 23 s h o w s th e d e ta ils o f th e a d c secti o n . t h e ad c ca n b e clo c k e d b y a n u m b er o f dif f er en t clo c k s o ur c e s t o co n t r o l t s a m p le ra t e . m c lk s e le c t io n fo r th e ad c is s e t b y i n t e r n al c l o c kin g c o n t rol reg i st er 1 (a ddr es s 0x76). th e ad c p r o v i d e a n o u t p u t w o rd o f u p t o 24 b i ts in r e s o l u tio n in tw os co m p le- m e n t fo r m a t . th e o u t p ut w o r d ca n b e r o ut e d to ei o u t p u t po r t s, th e sa m p le ra t e co n v e r t e r , o r th e s p d i f d i gi ta l tra n sm i t t e r . p ll2 inte rnal p ll1 inte rnal mclki xin reg 0x76 bits 4?2 dir p ll (2 5 6 f s ) reg 0x6f bits 1?0 04577-0-003 dir p ll (5 1 2 f s ) adc mclk divider adc mclk adc f i gure 23. cl ock p a th control o n the a d c programmabl e gain amplifier (pga) the i n p u t o f t h e r e co r d cha n nel fe a t ur es a pg a t h a t con v er t s t h e sin g l e -e n d e d sig n al t o a dif f er en t i a l sig n al , w h ich is a p pli e d to t h e an a l o g - mo d u l a tor of t h e a d c . t h e p g a c a n b e p r og ra mm e d t o a m p l if y a sig n a l b y u p t o 24 db in 0.5 db in cr e m e n ts. f i g u r e 24 s h o w s t h e s t r u c t ur e o f t h e pga cir c ui t . 4k ? to 64k ? 125 ? capxn external capacitor (1nf npo) vref to modulator external capacitor (1nf npo) capxp external capacitor (1nf npo) 8k ? 8k ? 04577-0-004 4k ? 125 ? f i g u re 24. pg a b l o c k d i ag r a m analog -? m o dul ator the a d c fe a t ures a s e cond-o r der , m u l t i b i t , - m o d u l a t o r . th e in p u t fe a t ur es t w o in teg r a t o r s i n ca s c ad e fol l o w e d b y a f l a s h co n v er t e r . this m u l t ib i t o u t p u t is dir e c t e d t o a s c ra m b ler , fol l o w e d b y a d a c fo r l o o p fe edb a c k . t h e f l a s h a d c o u t p a l s o co n v er te d f r o m t h er m o m e ter co d i n g to b i n a r y co din in p u t as a 5 - b i t w o r d t o t h e de ci ma t o r . f u t i s g fo r i gur e 2 5 sh o w s t h e ad c b l o c k di a g ra m. the a d c a l s o fe a t ur es i ndep e nden t dig i t a l volum e con t r o l f o r th e lef t and r i g h t c h a n n e ls. th e v o l u m e con t r o l co n s is ts o f 256 lin e a r st eps, wi t h each s t ep r e d u cin g t h e dig i tal o u t p u t co des b y 0.39%. e a c h c h a n ne l a l s o has a p e a k det e c t o r tha t r e co r d s t h e p e a k le v e l o f t h e i n p u t sig n al . th e p e ak de t e c t o r re g i ste r i s cl e a re d by re a d i n g it . a dc mcl k amc (reg 0x63 bit-7) multibit ? ? modulator decimator hpf peak detect v o l u m e o n t r o l 04577-0-005 c sinc^5 half-band filter modulator clock (6.144mhz max) 384khz 768khz sinc compensation 192khz 384khz half-band filter 96khz 192khz 48khz 96khz 2 4 d i ag r a m f i g u re 25. a d c b l o c k
ADAV801 rev. 0 | page 16 of 56 alc) at e aximum front end gain. olume adc is still present at the output of the adc, but scaled by a value determined by the volume control register. the alc block has two functions, attack mode and recover mode. recovery mode consists of three settings: no recovery, normal recovery, and limited recovery. these modes are discussed in the following sections. figure 26 is a flow diagram of the alc block. when the alc has been enabled, any changes made to the pga or alc settings are ignored. to change the functionality of the alc, it must first be disabled. the settings can then be changed and the alc re-enabled. attack mode when the absolute value of the adc output exceeds the level set by the attack threshold bits in alc control register 2, attack mode is initiated. the pga gain for both channels is reduced by one step (0.5 db). the alc then waits for a time determined by the attack timer bits before sampling the adc output value again. if the adc output is still above the threshold, the pga gain is reduced by a further step. this procedure continues until the adc output is below the limit set by the attack threshold bits. the initial gains of the pgas are defined by the adc left pga gain register and the adc right pga gain register, and they can have different values. the alc subtracts a common gain offset to these values. the alc preserves any gain differ- ence in db as defined by these registers. at no time do the pga gains exceed their initial values. the initial gain setting, therefore, also serves as a maximum value. the limit detection mode bit in alc control register 1 deter- mines how the alc responds to an adc output that exceeds the set limits. if this bit is a 1, then both channels must exceed the threshold before the gain is reduced. this mode can be used to prevent unnecessary gain reduction due to spurious noise on a single channel. if the limit detection mode bit is a 0, the gain is reduced when either channel exceeds the threshold. n is not recovered until the alc has been reset, either r by is in reduction unnecessarily. ormal recovery mode normal recovery mode allows for the pga gain to be recovered, provided that the input signal meets certain criteria. first, the alc must not be in attack mode, that is, the pga gain has been sufficiently such that the input signal is below the level set by the attack threshold bits. second, the output result from the adc must be below the level set by the recovery threshold bits in the alc control register. if both of these criteria are met, the gain is recovered by one step (0.5 db). the gain is incremen- tally restored to its original value, assuming that the adc output level is below the recovery threshold at intervals determined by the recovery time bits. if the adc output level exceeds the recovery threshold while the pga gain is being restored, the pga gain value is held and does not continue restoration until the adc output level is again below the recovery threshold. once the pga gain is restored to its original value, it is not changed again unless the adc output value exceeds the attack threshold and the alc then enters attack mode. care should be taken when using this mode to choose values for the attack and recovery thresholds that prevent excessive volume modulation caused by continuous gain adjustments. limited recovery mode limited recovery mode offers a compromise between no recov- ery and normal recovery modes. if the output level of the adc exceeds the attack threshold, then attack mode is initiated. when attack mode has reduced the pga gain to suitable levels, the alc attempts to recover the gain to its original level. if the adc output level exceeds the level set by the recovery threshold bits, a counter is incremented (gaincntr). this counter is incremented at intervals equal to the recovery time selection, if the adc has any excursion above the recovery threshold. if the counter reaches its maximum value, determined by the gaincntr bits in alc control register 1, the pga gain is deemed suitable and no further gain recovery is attempted. whenever the adc output level exceeds the attack threshold, attack mode is reinitiated and the counter is reset. automatic level control ( the adc record channel features a programmable automatic level control block. this block monitors the level of the adc output signal and automatically reduces the gain, if the signal the input pins causes the adc output to exceed a preset limit. this function can be useful to maximize the signal dynamic range when the input level is not well defined. the pga can b used to amplify the unknown signal, and the alc reduces the gain until the adc output is within the preset limits. this results in m because the alc block monitors the output of the adc, the volume control function should not be used. the adc v control scales the results from the adc, and any distortion caused by the input signal exceeding the input range of the no recovery mode by default, there is no gain recovery. once the gain has bee reduced, it y reduced by toggling the alcen bit in alc control register 1 o writing any value to alc control register 3. the latter option more efficient, because it requires only one write operation to reset the alc function. no recovery mode prevents volume modulation of the signal caused by adjusting the gain, which can create undesirable artifacts in the signal. the gain can be reduced but not recovered. therefore, care should be taken that spurious signals do not interfere with the input signal, because these might trigger a ga n
ADAV801 rev. 0 | page 17 of 56 l e r a t e - e ca us e i t a l u t r e d u ce s th e o v e r sa m p li n g ra ti o , c ted o g e n e ra t e a s e p a ra t e 12.288 m h z e a t selecting a s a m p the o u t p u t s a m p le ra t e o f the ad c is al wa ys ad c m c lk/256, as sh o w n in f i g u r e 23. b y defa u l t, th e ad c m o d u l a t o r r u n s a t ad c m c l k /2. w h en t h e ad c m c lk exceeds 12.288 mh z, t h e a d c mo d u l a tor s h ou l d b e s e t to r u n a t a d c mc l k / 4 . t h i s is ac hieved b y s e t t in g the am c (ad c m o d u la to r c l o c k) b i t in t h e ad c c o n t rol reg i st er 1. t o co m p e n s a t e fo r t h e r e d u ce d m o d u l a t o r clo c k s p e e d , a dif f er en t s e t o f f i l t ers a r e us e d i n t h e de cim a to r s e c t i o n en sur i n g t h a t t h e s a m p le r a te r e ma in s th e sa m e . the amc b i t can a l s o b e us e d to b o ost t h e th d + n p e r f o r m a n c e o f t h e ad c a t t h e exp e n s e o f d y na mic ran g e . th e im p r o v emen t is typ i cal l y 0.5 db t o 1.0 db an d wo rks, b se lectin g t h e lo w e r m o d u la t o r ra t e r e d u ces the a m o u n t o f d i g n o i s e , im p r o v in g t h d + n , b t h er efo r e r e d u ci n g t h e d y namic ra n g e b y a co r r es p o n d i n g amou n t . f o r b e st p e r f or m a n c e of t h e a d c , a v oi d u s i n g s i m i l a r f r eq uen c y c l o c ks f r o m s e p a ra t e s o ur ces in t h e ad a v 801. f o r exa m p l e , r u nnin g th e ad c f r o m a 12.288 m h z c l o c k co nn e t o m c lki an d usin g th e p l l t c l o c k f o r th e d a c ca n r e d u ce t h e p e r f o r m a nce o f th e ad c. this is d u e t o t h e in terac t io n o f t h e clo c ks, w h ich ge n e ra te b f r eq uen c ies tha t ca n a f f e c t t h e cha r g e o n the s w i t c h ca p a c i t o rs of t h e an a l o g i n put s . wait for sample wait for sample wait for sample decrease gain by 0.5db and wait attack time is sample greater than attack threshold? i s a b o threshold? is a recovery mode enabled? s a m p l e v e a t t a c k are all samples below recovery threshold? has gain been fully restored? yes yes no yes yes yes no no normal recovery increase gain by 0.5db wait recovery time limited recovery attack mode 04577- 0- 006 is sample above attack threshold? are all samples below recovery threshold? has gain been fully restored? is gaincntr at maximum? yes no no yes yes yes no no increase gain by 0.5db no increment gaincntr no no no has recovery time been reached? has recovery time been reached? f i g u re 26. a l c f l o w d i ag r a m
ADAV801 rev. 0 | page 18 of 56 p a ir 2 8 s t eps d e d to r e m o v e hig h e noi s e d n a l o p a m ps, which mig h t dra w m o r e tha n 50 a or ha v e d y na mic lo ad cha n g e s, ext r a b u f f er in g s h o u ld b e us e d t o p r es er v e t h e q u ali t y o f th e ad a v 801 r e f e r e n c e . t h e d i g i tal in p u t da t a so ur ce f o r th e d a c ca n b e se lect e d f r o m a n u m b er o f a v ai la b l e s o ur ces b y p r og ra mmin g t h e a p p r o p r i a t e bit s i n t h e d a t a p a t h c o n t ro l re g i ste r . f i g u re 2 7 show s how t h e d i gi ta l d a ta s o u r c e a n d th e m c l k s o u r c e f o r t h e d a c a r e s e le c t e d . e a ch d a c has a n i n de p e nden t vol u me r e g i ster g i vin g 256 s t eps o f co n t r o l , wi th each st ep g i vin g a p p r o x ima t e l y 0.375 db o f a t te n u a t ion. n o te t h a t t h e d a cs a r e m u te d b y defa u l t to p r ev e n t un w a n t ed po ps , c l i c k s , a n d o t h e r n o ise s f r o m a p pe a r i n g o n the o u t p u t s while t h e ad a v 801 is bein g c o nf igur ed . e a c h d a c a l s o h a s a p e a k - l e v e l re g i s t e r t h a t re c o rd s t h e p e a k v a lu e o f t h e dig i t a l a u di o da t a . r e adi n g t h e r e g i st er cle a rs t h e p e a k . e l e c t i n g a sample rat e c o r r e c t op e r a t i o n of p on t h e d a t a r a te s ) b y 2. this p r e v en ts t h e d a c en g i n e f r o m r u nni ng to o f a s t . t o c o m p e n s a te for t h e re d u c e d mc l k r a t e , t h e in t e r p ol a t o r sh ou ld be s e lec t e d to o p era t e in 4 (d a c m c lk = 128 f s ). simi lar co m b in a t io n s ca n b e s e le c t e d fo r dif f er en t sa m p l e ra t e s . da c s e c t i o n s the ad a v 801 has tw o d a c cha n n e ls a r ra n g e d as a s t er e o wi t h sin g le -e n d e d a n alog o u t p u t s. e a c h c h a n ne l has i t s own indep e n d en tl y p r og ra mma b l e a t t e n u a t o r , ad j u s t a b l e i n 1 o f 0.375 db p e r s t ep . th e d a c c a n r e cei v e da t a f r o m th e p l a y ba ck o r a u xili a r y i n p u t po r t s, th e s r c , th e a d c , o r th e d i r . e a ch a n a l o g o u tp u t p i n si ts a t a dc le vel o f vre f , a n d s w i n gs 1.0 v r m s f o r a 0 db dig i tal in p u t sig n al . a sin g le o p a m p thir d- o r der ext e r n al l o w-p a s s f i l t er is r e co mmen f r e q uen c y n o is e p r es en t on t h e o u t p ut p i n s . n o t e t h a t t h e us e of o p a m ps wi t h lo w sle w ra te o r lo w b a n d wi d t h can c a us e hig h f r e q uen c y n o is e a nd ton e s to fold do w n i n to t h e a u dio b a nd . c a r e s h o u ld b e tak e n in s e le c t in g th es e co m p on e n ts. t h e fil t d an d fil t r p i n s sh o u ld be b y pas s e d b y ext e r n al c a p a c i tors to a g nd . t h e f i l t d pi n i s u s e d to re d u c e t h o f th e i n t e rn al d a c b i as ci r c ui tr y , th e r e b y r e d u ci n g th e d a c o u t p u t n o is e . th e v o l t a g e a t t h e vref p i n, fil t r , c a n be us e t o b i as ext e r n al o p a m ps us ed to f i l t er th e o u t p u t sig n als. f o r a p plic a t ion s in w h ich t h e fil t r is r e q u ir e d t o dr i v e ext e r t h e d a c i s d e p e nd e n t u p r o v i d ed t o th e d a c , th e m a st er c l oc k a p p l i e d t o th e d a c , a n d t h e s e l e c t e d i n te r p ol a t i o n r a te. b y de f a u l t , t h e d a c a ssu me s t h a t th e m c l k ra te is 256 tim e s t h e s a m p le ra t e , whic h r e q u ir es a n 8-tim e s o v ers a m p lin g r a t e . this co m b ina t ion is s u i t ab le f o r s a m p l e r a te s of up to 4 8 k h z . f o r a 96 kh z da ta ra te tha t has a 24.576 mh z m c l k ( 2 5 6 f a s soci a t e d wi th i t , th e d a c m c l k d i v i d e r sh o u ld be se t t o divide t h e mcl k 04577-0-007 p ll2 inte rnal p ll1 inte rnal mclki xin reg 0x76 bits 7 ? 5 reg 0x65 bits 3?2 reg 0x63 bits 5 ? 3 dir p ll (2 5 6 f s ) dir p ll (5 1 2 f s ) dir playback auxiliary in adc mclk divider dac mclk dac dac input f i gure 2 7 . clo c k a n d d a ta pa th c o ntr o l on the d a c multibit - ? modulator interpolator dac dac t o z e r o f l a g p i n s from dac datapath multiplexer volume/mute control peak detector zero detect to control registers output 04577-0-008 f i g u re 28. da c b l o c k d i ag r a m analog
ADAV801 rev. 0 | page 19 of 56 v ervie w l e r a te c o n v e r s i o n , d a t a c a n b e co n v o r a t t s a m r a t e s. the sim o n is t o us e a zer o -o r d e r h o ld b e twe e n t h e tw o m , t2 tio n al . a t f s_o u t a r e r e pea t ed o r d r o p ped , p r o d u c i n g p l i n g pro c e s s . t r s_o u t a t e d i m a g es f r o m t h e s i n(x)/x na t u r e o f t h e zer o - o r d e es) o f th e zer o - o r der h n f i ni te h e ra t i o o f t2 t o t 1 i r o m t h e n n e ver b e e l im ina t e d . t h e er r o r ca n b e h e h e t u al l y in t e r p ola t ed b y a f a c t o r o f 2 20 . sample r a te c o nver ter (src ) fu nc tional o d u r i ng a s y n ch r o nou s s a m p er t e d a t t h e s a me s a m p le r a t e dif f er en p l e p lest a p p r o a c h t o a n as yn c h r o n o us s a m p le ra te co n v e r s i s a m p lers, as sh o w n in f i gur e 29. i n an asy n chr o n o us sy st e is n e v e r eq ual to t 1 , n o r is the ra tio betw een t2 a n d t 1 r a a s a re su lt, s a m p l e s a n e r r o r i n t h e re s a m the f r e q uen c y do ma in sh o w s th e wide side lob e s t h a e s u l t f r o m t h i s e r r o r w h en t h e s a m p l i n g o f f is co n v olv e d w i t h t h e a t t e n u r h o ld . th e ima g es a t f s_i n (dc signal ima g o ld a r e i l y a t t e n u a t e d . b e c a us e t s a n ir ra t i o n a l n u m b er , t h e e r r o r r e su l t in g f re s a m p l i ng a t f s_o u t ca sig n if ica n t l y r e d u ce d , h o we v e r , t h r o ug h in t e r p ol a t io n o f t in p u t d a t a a t f s_i n . t h er efo r e , t h e s a m p le ra t e con v er t e r in t ad a v 801 is con c ep 04577-0-009 spectrum of f s_out sampling f s_out 2 f s_out frequency response of f s_out convolved with zero-order hold spectrum zero-order hold f s_in = 1/t1 f s_out = 1/t2 original signal sampled at f s_in sin(x)/x of zero-order hold s p e c t r u m o f z e r o - o r d e r h o l d o u t p u t out in f i gure 29. zero - o rder ho ld u s e d b y f s_ o u t to resam p l e d a ta f r om f s_i n con c e p tua l h i g h i n te r p ola t i o n m o de l g y t o s u p p r es s t h e s t h i n te r p o l a t i o n of t h e i n put d a t a by a f a c t or of 2 20 in v o lv es plac i n (2 20 ? 1) sa m p l e s bet w een ea ch f s_i n s a m p le . f i gur e 30 s h o w s b o t h th e ti m e d o m a i n a n d th e f r e q u e n c y d o m a i n o f in t e r p ol a t ion b y a fac t o r o f 2 20 . c o n c e p t u a l l y , i n t e r p o l a t i o n b 2 20 in v o l v es t h e s t eps o f zer o -st u f f i n g (2 20 ? 1) n u m b er o f sa m p l e s be t w een ea c h f s_i n s a m p le a nd con v olv i n g t h is in t e r p ol a t e d sig n al w i t h a dig i t a l lo w-p a s s f i l t e r i m a g e s . i n th e tim e d o m a in , i t ca n be e e n a t f s_o u t se l e ct s t h e cl o s est f s_i n 2 20 s a m p l e f r om t h e z e ro - o rd e r ho l d , a s opp o s e d t o th e n e a r e s t f s_i n s a m p le in t h e c a s e o f n o in t e r p ola t ion. this s i g n i f i c an t l y re du c e s t h e re s a m p l i ng e r ror . 04577-0-010 f s_in f s_out in out interpolate by n low-pass filter zero-order hold time domain of f s_in samples time domain output of the low-pass filter time domain of f s_out resampling time domain of the zero-order hold output f i g u re 30. sr c ti m e d o ma in i n t h e f r e q ue n c y do ma in sh ow n in f i gur e 31, t h e i n t e r p ol a t ion exp a n d s t h e f r e q uen c y a x i s o f t h e zer o -o r d er hold . the ima g es f r o m t h e i n t e r p o l at i o n c a n b e s u f i c i e n t l y at t e n u at e d b y a g o o d lo w-p a s s f i l t er . the ima g es f r o m t h e zer o -o r d er h o ld a r e n o w pu she d by n p o i n t h e f a f a c t or of 2 20 clos er t o t h e inf i ni te a t ten u a t i o of t h e z e ro - o rd e r ho l d , w h i c h i s f s_i n 2 20 . the i m a g es a t t h e zer o -o r d er h o l d a r e t h e det e r m i n in g fac t o r fo r t h e f i de li ty o f t output a t f s_o u t . 04577-0-011 f s_in f s_in 2 20 f s_in 2 20 f s_in 2 20 f s_in f s_out in out interpolate by n low-pass filter zero-order hold frequency domain of samples at f s_in frequency domain of the interpolation frequency domain of f s_out resampling frequency domain after resampling sin(x)/x of zero-order hold f i g u re 31. f r equen c y d o m a in of t h e i n terpol at i o n and r e s a mp li ng
ADAV801 rev. 0 | page 20 of 56 t h e m p u t e d f r o m t h e zer o -o r d er f / f s_interp )/( f / f s_interp ) hardware model the o u t p u t r a t e o f t h e lo w-p a s s f i l t er in f i gur e 3 0 is t h e in t e r p ol a t ion ra t e : 2 20 192,000 kh z = 201.3 g h z sa m p l i n g a t a r a t e o f 201.3 gh z is c l ea rl y im p r ac tical , n o t t o m e n t ion t h e n u m b er o f t a ps r e q u ir e d t o c a lc u l a t e e a ch i n t e rp o l a t ed s a m p l e . h o w e v e r , b e c a u s e i n t e rp o l a t i o n b y 2 20 i n v o l v e s z e r o - s t u ffi n g 2 20 ?1 sa m p les betw e e n eac h f s_i n sa m p le , mo st of t h e m u lt i p l i e s i n t h e l o w-p a ss f i r f i lte r are b y ze ro . a f u r t h e r r e d u c t io n can b e r e a l i z e d , b e ca us e o n ly o n e i n ter p ola t e d s a m p le is ta k e n a t t h e o u t p u t a t th e f s_o u t r a te, s o on ly one co n v ol u t ion n e e d s to b e p e r f o r m e d p e r f s_o u t pe ri od i n s t ea d o f 2 20 co n v ol u t ion s . a 64-t a p fir f i l t er f o r eac h f s_o u t sa m p l e i s su f f i c i e n t to su pp re ss t h e image s c a u s e d b y t h e in te r p ol a t ion. on e dif f i c u l t y wi t h t h e ab o v e a p p r o a ch is t h a t t h e co r r e c t in t e r p ol a t e d s a m p le m u s t b e s e le c t e d u p o n t h e a r r i val o f u t . b e ca us e t h e ri od , th e l y p h a s e 26 , e al e d . a s t h e in p u t sa m p l e ra t e ri se s o v e r t h e o u t p u t s a m p l e r a t e , th e a n t i a l i a s i n g fi l t e r s cu t o ff fr e q u e n c y y s fifo b l o c k ad j u sts the lef t a nd r i g h t in p u t s a m p les an d o r es t h e m fo r t h e fir f i l t er s c t o t h e fifo b l o l s e r v o lo o p . t ion alin g t a l w o rs t- cas e ima g es c a n b e c o hol d f r e q u e nc y re sp ons e : ma x i m u m ima g e = s i n ( w h er e: f is t h e f r e q ue nc y o f t h e w o rs t- cas e i m a g e t h a t w o u l d b e 2 20 f s_in f s_in /2. f s_interp is f s_in 2 20 . the fol l o w in g wo rst-ca s e im a g e s w o u l d a p p e a r fo r f s_in eq ual t o 192 kh z: im a g e a t f s_interp ? 96 kh z = ?1 25.1 db im a g e a t f s_interp + 96 kh z = ?125.1 db f s_o er e ar e 2 20 pos s i b l e co n v o l u t i o n s pe r f s_o u t p a rri v a l o f th e f s_ o u t clo c k m u st b e m e asur e d w i t h a n a c c u rac y o f 1/201.3 gh z = 4.96 ps. m e as ur in g th e f s_o u t pe ri od w i th a c l oc k o f 201.3 gh z f r eq uen c y is c l ea rl y im p o s s ib le; ins t ead , s e v e ral co a r s e m e as ur em en ts o f the f s_o u t clo c k p e r i o d a r e made and av e r a g e d o v e r t i m e . an o t h e r dif f i c u l t y w i t h t h e ab ov e a p p r o a ch is t h e n u m b er o f co ef f i cien ts r e quir e d . b e c a us e t h er e a r e 2 20 pos s i b l e c o n v o l u - ti o n s w i t h a 64-ta p fir f i l t e r , th e r e m u s t be 2 20 po co ef f i cien ts f o r eac h t a p , which r e q u ir es a t o tal o f 2 c o e ffi - cien ts. t o r e d u c e t h e n u m b er o f co ef f i cien ts i n r o m, t h e sr c store s a s m a l l su b s e t of c o e f f i c i e n t s a n d p e r f or ms a h i g h ord e r in t e r p ol a t ion b e tw e e n t h e s t o r e d co ef f i cien ts. the ab o v e a p p r o a ch w o rks w h e n f s_o u t > f s_i n . h o w e v e r , w h e n th e o u t p u t sa m p le ra t e , f s_o u t , is les s tha n t h e in p u t s a m p le ra t e f s_i n , th e r o m sta r ti n g a d d r e s s, i n p u t da t a , a n d le n g th o f th c o n v o l u t i o n m u s t be s c m u s t b e lo w e r e d , b e ca us e t h e n y q u is t f r e q ue nc y o f t h e o u t p ut s a m p les is less t h a n t h e n y q u ist f r e q uen c y o f t h e in p u t s a m p les. t o m o v e t h e c u to f f f r e q uen c y o f t h e an t i ali a sin g f i l t er , t h e co ef f i cien ts a r e d y na mi ca l l y a l ter e d an d t h e le ngt h o f t h e co n v ol u t ion is i n cr e a s e d b y a fa c t o r o f (f s_i n /f s_o u t ). t h i s te c h n i qu e i s supp or te d by t h e f o u r i e r t r ans f or m prop e r t t h a t , i f f ( t ) i s f ( ) , t h e n f ( k t ) i s f ( / k ) . t h u s , t h e r a n g e o f d e ci ma ti o n i s lim i t e d b y th e size o f th e ra m. src architectu re the a r chi t e c t u r e o f t h e s a m p le ra t e c o n v er t e r is s h o w n in f i gur e 32. th e s a m p le ra t e con v er t e r s t o n v ol u t ion c y c l e . th e f s_i n co u n t e r p r o v ides t h e wr i t e addr es s c k an d t h e ram p in p u t t o t h e di g i t a the r o m st o r es t h e co ef f i cien t s fo r t h e fir f i l t er co n v ol u a nd p e r f o r m s a hig h o r der i n ter p ola t ion b e tw e e n t h e sto r e d co ef f i cien ts. the s a m p le r a t e r a t i o b l o c k m e as ur e s t h e s a m p le ra t e fo r d y nami cal l y al t e r i n g t h e r o m co ef f i cien ts and s c o f t h e fir f i l t er len g t h as we l l a s t h e i n p u t d a t a . the dig i se r v o loo p a u t o m a ti call y tra c k s th e f s_i n an d f s_o u t sa m p l e ra t e s a nd p r o v ides t h e r a m and rom st a r t a d d r ess e s fo r t h e st a r t of t h e fir f i l t e r c o n v ol u t ion. 04577-0-012 right data in left data in fifo rom a rom b digital servo loop f s_in counter rom c rom d f s_in f s_out sample rate ratio sample rate ratio external ratio interp fir filter l/r data out high order f i gure 32. a r ch itec tur e of the s a mp le r a te co n v er ter the fifo r e ceiv es t h e lef t and r i g h t in p u t da t a a nd ad j u s t s t h e a m p l i t u d e o f th e d a ta f o r b o t h th e s o ft m u ti n g o f t h e s a m p l e ra t e co n v e r t e r a n d th e scali n g o f th e i n p u t da ta b y th e sa m p le ra t e ra t i o b e fo r e s t o r in g t h e s a m p les in t h e r a m. th e in pu t da t a is s c aled b y t h e s a m p le ra t e ra tio , bec a us e , as t h e fir f i l t er le n g th o f th e co n v o l u t i o n in cr e a se s, so d o e s th e a m p l i t ud e o f t h e c o n v o l ut i o n output . t o ke e p t h e output of t h e f i r f i lte r f r om sa t u ra ti n g , th e in p u t da t a i s scaled d o wn b y m u l t i p l y i n g i t b y (f s_ o u t /f s_i n ) wh en f s_o u t < f s_i n . th e fifo als o s c ales t h e i n p u t da ta f o r m u t i n g a n d unm u ti n g o f th e s r c. the ram in t h e fifo is 512 w o r d s deep f o r b o th lef t an d r i g h t cha n n e ls. an o f fs et t o t h e wr i t e addr es s p r o v ide d b y t h e f s_i n co un t e r i s a d d e d t o p r ev en t t h e ra m r e a d po in t e r f r o m o v erla p p i n g t h e wr i t e addr es s. th e mini m u m o f fs et o n t h e s r c is 16 s a m p les. h o w e ver , t h e g r o u p del a y an d m u te-i n r e g i ster ca n be us e d t o in cr eas e this o f fs et.
ADAV801 rev. 0 | page 21 of 56 u t s a m p les adde d t o t h e wr i t e p o in t e r o f t h e (512 ? 16)/64 ta ps = 7.75 f o r shor t g r oup d e l a y a n d (512 ? 64)/64 ta ps = 7 fo r l o ng g r o u p del a y . o o f f s_i n /f s_o u t the n u m b er o f in p fifo o n th e s r c is 16 p l us b i t 6 t o b i t 0 o f th e g r o u p de la y r e g i st er . this fe a t ur e is us ef u l in va r i sp e e d a p pli c a t io n s t o p r e v en t t h e r e ad p o i n t e r t o t h e fifo f r o m r u n n in g a h e a d o f t h e wr i t e p o i n ter . w h e n s e t, bi t 7 o f t h e g r o u p del a y a nd m u te -in r e g i s t er s o f t - m ut es t h e s a m p le r a t e . i n cr e a si n g t h e o f fs et o f t h e wr i t e addr ess p o in t e r is us ef u l fo r a p plic a t io n s i n w h ich sma l l c h a n g e s in the s a m p le ra t e ra tio betw een f s_i n a nd f s_o u t are ex p e c t e d . t h e max i m u m de ci ma t i on ra te can b e ca lc u l a t e d f r o m th e ram w o r d d e p t h a n d th e gr o u p d e la y a s the dig i tal s e r v o lo o p is es s e n t ial l y a ra m p f i l t er tha t p r o v ides t h e i n i t ia l p o in ter t o t h e ad dr ess in r a m an d ro m fo r t h e st a r t o f t h e fir con v ol u t io n. t h e r a m p o in t e r is t h e in teger o u t p u t o f th e ra m p f i l t er , a n d t h e r o m i s th e f r a c ti o n al pa r t . t h e dig i t a l s e r v o lo o p m u s t p r o v ide exce l l en t r e je c t i o n o f ji t t er on th e f s_i n an d f s_o u t clo c ks, as w e l l as m e asur e t h e a r r i va l o f t h e f s_o u t clo c k w i t h in 4.97 ps. t h e dig i t a l s e r v o lo o p a l s o di vide s th e f r a c ti o n al p a r t o f th e ra m p o u t p u t b y th e ra ti t o d y na mi cal l y al t e r t h e r o m c o ef f i cien ts w h e n f s_i n > f s_o u t . 04577-0-013 dir p ll (2 5 6 f s ) iclk2 iclk1 reg 0x00 bits 1 ? 0 reg 0x76 bit 0 reg 0x76 bit 1 reg 0x62 bits 7? 6 dir p ll (5 1 2 f s ) dir playback auxiliary in adc mclki xin src mclk src output src src input pllint2 pllint1 f i gure 3 3 . clo c k a n d d a ta pa th c o ntr o l on the scr the dig i t a l s e r v o lo o p is im plem e n t e d wi t h a m u l t ira t e f i l t er . t o tt l e t h e d i g i t a l s e r v o l o op f i lte r more qu i c k l y up on s t ar tup or a adde d to t h e a m p le r a t e is e as o n a b le val u e , th e dig i t a l d u r i n g fas t m o de , t h e m u te_ o ut b i e er r o r e h e u a t c l ic k s g h t p r es l a u d i o t p u t o f e m u b i t 7 o f h e g r o u p d e l a y a n d r l t g e d t o h e mu a n b e n i n te r w h e n t h e src m h in g sa m p le ra t e o n v e l y . e /f s_i n ) 2 20 ra tio f o r s e cha n ge i n t h e s a m p le r a te, a fast m o d e has b e e n f i l t er . w h e n t h e dig i t a l s e r v o lo o p s t a r ts u p o r the s c h a n g e d , th e dig i tal s e r v o lo o p en t e rs fas t m o de t o ad j u s t and s e t t l e o n t h e n e w s a m p l e ra t e . u p o n se n s i n g th a t th e d i gi ta l s e r v o lo o p is s e t t lin g do wn t o a r ser v o lo o p r e t u rn s t o n o r m al (o r s l o w ) m o d e . t in t h e s a m p le ra t r e g i s t r i s a s s e r t ed t o l e t t s er kn o w t h o r p o p s m i b e e n t i n t h e dig i t a d a t a . th e o u t h e s r c can b te d b y ass e r t in g t m u te r e g i s t e un t i h e s r c has cha n s l o w m o de . t te_o u t b i t c s e t to ge ne r a te a r upt c h ange s to s l o w o de , in d i ca tin g th a t t e da ta i s be c r te d a c c u r a t e t h e f r e q u e nc y re sp ons e s of t h e d i g i t a l s e r v o l o op f o r f a s t mo d a nd slo w m o de a r e sh own i n f i gur e 34. th e f i r f i l t er is a 64-t a p f i l t er w h en f s_o u t f s_i n and i s ( f s_i n /f s_o u t ) 64 ta ps w h en f s_i n > f s_o u t . th e fir f i l t er p e r f o r m s i t s co n v ol u t ion b y lo adin g in t h e s t a r t i n g addr es s o f t h e r a m addr es s p o i n t e r and t h e r o m a d d r e s s po i n t e r f r o m th e di gi ta l se r v o loo p a t th e s t a r t o f th e f s_o u t p e r i o d . th e fir f i l t er t h e n s t eps t h r o ug h t h e r a m b y d e cr e m en tin g i t s a d d r e s s b y 1 f o r ea c h ta p , a n d th e r o m p o in t e r i n cr eme n ts i t s addr es s b y t h e (f s_o u t f s_i n > f s_ o u t or 2 20 fo r f s_o u t f s_i n . on ce t h e ro m addr es s r o l l s o v er , t h e co n v ol u t io n is com p lete d . 04577-0-014 frequency (hz) magnitude (db) 0 ?2 0 ?4 0 ?6 0 ?8 0 ?100 ?120 ?140 ?160 ?180 ?200 0.01 0.1 1 1 0 100 1k 10k 100k slow mode fast mode ?220 f i g u re 34. f r equen c y r e s p ons e of t h e d i g i t a l s e r v o l oop . f s_i n is t h e x - a x is, f s_o u t = 19 2 kh z, m a ster cl ock is 3 0 m h z the con v ol u t ion is p e r f o r m e d fo r b o t h t h e lef t a nd r i g h t cha n n e ls, an d t h e m u l t i p ly acc u m u la t e cir c ui t us e d fo r t h e co n v ol u t ion is sha r e d b e t w e e n t h e chan n e ls. t h e f s_i n /f s_o u t s a m p l e r a te r a t i o c i rc u i t i s u s e d to dy n a m c a l l y a l te r t h e i n t h e r o m w h e n f s_i n > f s_o u t . t h e r a t i o i s c a l c u l a t e d by c o m p ar i n g t h e output of an f s_o u t c o u n te r to t h e output of an f s_i n co un t e r . i f f s_o u t > f s_i n , th e ra t i o is h e l d a t one . u t , t h e s a m p le ra t e r a t i o is u p d a t e d , if i t is dif f er en t b y m o r e th a n tw o f s_o u t pe ri od s f r o m th e p r ev io u s f s_ o u t to f s_i n co m p a r is o n . th is is do ne t o p r o v ide s o m e h y st e r esis t o p r e v en t i co ef f i cien t s if f s_i n > f s_o th e f i l t e r le n g th f r o m oscilla t i n g a n d ca usi n g d i st o r ti o n .
ADAV801 rev. 0 | page 22 of 56 a n ex ter n a l pll sec t ion the ad a v 801 fea t ur es a d u al pll co nf igura t ion t o g e n e ra t e indep e n d en t sy stem clo c ks fo r asy n chr o n o us o p er a t io n. f i g u re 3 7 show s t h e bl o c k d i ag r a m of t h e pl l s e c t i o n . t h e pl l gen e r a t e s t h e i n t e r n a l a nd sy st e m clo c ks f r o m a 27 mh z clo c k. this clo c k is ge n e r a te d ei t h er b y a cr y s t a l co nne c t e d b e tw e e n xin and x o u t , as sh own i n f i gur e 35, o r f r o m clo c k s o ur ce conn e c te d dir e c t ly to xin. a 54 m h z clo c k can also be used , i f t h e in t e rn al c l ock d i vi der i s used . cc xta 04577-0-015 l xin xou t f i gure 35. cr ystal connection b o t h plls (pll 1 a nd pll2) can b e p r o g r a mme d i n de p e n d e n t l y a nd can accomm o d a t e a ra n g e o f s a m p lin g ra t e s (32/44.1/48 kh z) wi th s e lec t a b le sys t em c l o c k o v ers a m p ling ra t e s o f 256 a nd 384. h i g h er o v ers a m p lin g r a t e s ca n als o be s e le c t ed b y enab ling th e dou b lin g o f th e s a m p lin g ra te t o g i v e 512 o r 768 f s ra tios. n o t e tha t this op tio n als o al lo ws o v ers a m p lin g ra tios o f 256 o r 384 a t do ub le s a m p l e r z. the pll o u t p u t s ca n b e r o ut e d in t e r n a l ly t o ac t as clo c k s o ur ce s fo r t h e o t h , an d s o o n . th e o u t p u t s o f t h e p lls a r e als o a v a i lab l e on t h e t h r e e s y sclk p i n s . f i gur e 38 s h o w s h o w t h e p l l s c a n be co nf igur e d t o p r o v ide t h e s a m p ling clo c ks. mclk selection a t e s o f 64 / 8 8 . 2 / 9 6 k h e r com p on e n t b l o c ks such as t h e ad c, d a c table 7. pll frequency selection options pll sample rate ( f s ) normal f s do uble f s 1 32/44.1/48 khz 256/384 f s 512/768 f s 64/88.2/96 khz 256/384 f s 2a 32/44.1/48 khz 256/384 f s 512/768 f s 64/88.2/96 khz 256/384 f s 2b same as f s sel e c t ed 512 f s for pll 2a 512 f s the p lls r e q u ir e s o m e exter n al co m p on e n ts t o o p era t e co r r e c t l y . th es e c 6 , fo r m a lo o p p and t y o w s d as mast er clo c ks r t e ad a v 8 0 1 e d a c o r ad c. e nd g r o p i n s , w h ich sh o u ld b e l t e l ectri s e f r o m b e i n g n v o upl i n ns . o m p on e n ts, sho w n i n f i gur e 3 f i l t er t h a t in teg r a t es t h e c u r r en t p u ls es f r o m a cha r g e p u m p r o d uces a v o l t a g e t h a t is us e d t o t u n e t h e v c o . g o o d q u ali ca p a c i t o rs, s u c h as p p s f i lm, a r e r e co mm ende d . f i gur e 37 s h a b l o c k d i a g ram o f t h e pll s e c t i o n, incl uding m a st er clo c k s e le c t io n. f i gure 38 sh o w s h o w t h e clo c k f r e q uen c ies a t t h e cl o c k output pi ns , s y s c l k 1 to s y s c l k 3 , a nd t h e i n te r n a l p l l c l o c k v a l u e s , p l l 1 a n d p l l 2 , a r e s e l e c t e d . the clo c k n o de s, pll1 an d pl l2, ca n b e us e f o h e o t h e r b l o c k s i n t h s u c h as t h t h p l l h a s s e p a r a te sup p ly a u n d a s c e a n a s pos s i b l e t o p r ev en c al n o i c o e r te d i n to c l o c k jitte r b y c g on to t h e l o op f i lte r p i 04577-0-016 pll block 3.3k ? pll_lfx 100nf avdd 6.8nf fi g u r e 3 6 . p l l lo o p fi l t e r 04577-0-017 mclki r e g 0 x b i t mclko reg 0x74 bit 5 g 0 x 7 4 bit 4 reg 0x78 bit 6 7 8 7 phase detector and loop filter pll1 sysclk1 sysclk2 sysclk3 pll_lf2 xout r e xin pll_lf1 2 2 vco n output scaler n1 phase detector and loop filter pll2 vco n output scaler n2 output scaler n3 s e c t i o n b l o c k d i ag r a m f i g u re 37. pll
ADAV801 rev. 0 | page 23 of 56 04577-0-018 pll1 mclk pll2 mclk 48khz 32khz 44.1khz 256 384 reg 0x75 bits 3?2 r e g reg 0x75 bit 1 0 x 7 5 bit 0 reg 0x77 bit 0 pll1 pllint1 sysclk1 2 fs1 2 reg 0x75 bit 5 reg 0x75 bit 4 reg 0x77 bits 2? 1 x 7 7 ? 6 pll2 pllint2 sysclk2 r e g 0 b i t s 5 reg 0x74 bit 0 sysclk3 48khz 32khz 44.1khz 256 384 2 fs2 fs3 2 2 256 512 f i gure 38. pll c l oc k i ng s c he me spdif tr ansmit t er and receiver the ad a v 801 co n t a i n s an in t e g r a t ed s p d i f tra n smi t t e r and re c e ive r . t h e t r a n s m it te r c o ns i s t s of a s i ng l e output pi n , dit o u t , o n w h ich t h e b i ph as e en c o de d da t a a p p e a r s. the s p d i f t r a n smi t t e r s o ur ce can b e s e le c t e d f r o m t h e dif f er en t b l oc k s m a k i n g u p th e a d a v 801. a d d i ti o n all y , th e c l ock so ur ce f o r th e s p d i f tra n sm i t t e r ca n b e se lect e d f r o m th e v a ri o u s c l ock s o ur ces a v a i la b l e in t h e ad a v 8 01. the r e cei v er us es tw o p i n s , d i rin and d i r_l f . d i rin accep t s t h e spdif in put d a t a st r e am. t h e diri n p i n c a n b e co nf igur e d t o accep t a dig i t a l in p u t le ve l, as def i n e d i n t h e s p e c if ic a t io n s s e c t io n, o r a n in p u t sig n al wi t h a p e a k -t o-p e a k lev e l o f 200 mv minim u m, as def i n e d b y th e ie c60958-3 s p ec if ica t ion. d i r_lf is a lo o p f i l t er pin, r e q u ir e d b y t h e i n t e r n a l pll, w h ich is us e d to r e co v e r th e c l oc k f r o m th e s p d i f d a t a s t r e a m . the co m p on en ts s h own in f i gu r e 42 f o r m a lo o p f i l t er , whic h in teg r a t es t h e c u r r en t p u ls es f r o m a cha r g e p u m p an d p r o d uc es a v o l t a g e tha t is us ed t o t u n e t h e v c o o f t h e c l o c k r e co v e r y pll. t h e r e co ve r e d a u dio d a t a and a u dio clo c k ca n b e r o ute d to th e dif f er en t b l o c ks o f th e ad a v 801, as r e q u ir e d . f i gur e 39 show s a c o n c e p tu a l d i ag r a m of t h e di r i n bl o c k . c* 04577-0-019 spdif * external capacitor is required only for variable level spdif inputs. comparator reg 0x74 bit 4 dirin dc level spdif receiver f i gure 39. dirin b l ock 04577-0-020 dit input dit playback auxiliary in src reg 0x63 bits 2? 0 adc channel status and user bits dir ditout f i gure 4 0 . di g i ta l o u tput t r ansmi t t e r bl ock dia g r a m 04577-0-021 dir dirin audio data recovered clock channel status/ user bits f i gure 4 1 . di g i ta l input r e c e iver b l oc k d i ag r a m
ADAV801 rev. 0 | page 24 of 56 04577-0-022 dir block d i r _ l f 100nf 3k ? avdd 6.8nf fi g u r e 4 2 . o n e l d i g u d i o t a n d ad a v 801 ca n r e cei v e and tra p d i f , aes/eb u 9 5 8 s e r i al str d , / eb u is a p r o f e 9 5 8 h a s s u m er a nd p r o t a she e t is t e nd e d to f e r d s. c o n e f u l l sp e c if ica t ion e dig i t a a u dio co n t r o l info e - ma r k d . this e n co din g m e c o n t e n t o f t h e i t t e d sig n al . a s c i n t h e al da ta en d u p w i t h m e b i p h a s e- e n co de d d a t a , w h i l e 0s i n t a do n o t. n o te e b i p h a s e- m a r k en cod a tra n si ti o n e n b i t b o u nda d i r lo o p fi l t e r c o m p n t s s e r i a i t a l a t r ans m is s i on s a r d s the n smi t s , an d i e c - e a m s. s p d i f is a co n s u m er a u dio s t anda r a nd aes s sio n al a u dio s t anda r d . i e c - b o t h con f essio n a l def i ni t i on s. th is d a not i n u l l y d e f i ne or t o prov i d e a tuto r i a l for t h e s st a n d a t ac t t h e in ter n a t i o na l st anda r d s- s e t t i n g b o d i e s fo r t h s . a l l t h es l a u dio co m m un ica t ion s c h e m e s en co de a u d i o d a t a and r m a t io n usin g t h e b i phas m e t h o t h o d min i mi zes t h e d c tra n s m a n b e s e en f r o m f i gur e 43, 1 s o r i g i n i d c e l l tra n si ti o n s i n th ma r k t h e o r ig ina l d a th a t t h e d s da ta alw a ys h a b e tw e r i es. 01 1 1 00 04577-0-023 clock ( 2 times bit rate) biphase-mark data data f i gure 43. biph as e - mark e n coding dig i t a l a u dio - c o mm u n i c a t io n s c h e m e s us e p r e a m b les to dist in gui s h am on g cha n n e ls (ca l le d sub f r a m e s) a nd am o n g lo n g er -t er m con t r o l inf o r m a t io n b l o c ks (cal le d f r a m es). pre a mbl e s are p a r t i c u l ar b i ph a s e - m a r k p a t t e r ns , w h i c h c o n t a i n en co ding vio l a t i o n s t h a t a l lo w t h e r e ce i v er to uniq uely r e cog n ize t h e m . th e s e p a t t er n s a nd t h eir r e l a t i on s h i p t o f r a m es a nd sub f r a m e s a r e sh own i n t a b l e 8 an d f i gur e 44. table 8. biphas e-mark e n code preamble biphase patter n s channel x 11100010 or 00 011101 left y 1 1 1 0 0 1 0 0 o r 0 0 011011 right z 11101000 or 00 010111 left and cs block start xy z y x y 04577- 0 2 4 preambles left ch frame 191 frame 0 frame 1 right ch left ch right ch left ch right ch sub- frame sub- frame 0- fi g u r e 4 4 . p r e a m b l e s , fra m e s , a n d s u b f ra m e s the b i phas e-mark e n co din g viola t ion s a r e sh o w n in f i gur e 45. n o t e tha t all th r e e p r ea m b le s in c l ud e en codi n g v i o l a t i o n s . or dina r i ly , t h e b i ph as e - ma rk e n din g met h o d r e su l t s i n a p o la r i ty t r a n s i t i o n c o b e twe e n b i t b o u nda r i es. 11 1 0 00 1 0 11 1 0 01 0 0 11 1 0 10 0 0 04577-0-025 preamble x preamble y preamble z f i g u re 45. p r ea mb l e s the s e r i a l dig i t a l a r ga nize d e bits u dio co m m u n ica t io n s c he me is o usin g a f r a m e and s u b f ra me con s t r uc t i o n . th e r e a r e tw o sub f r a me s p e r f r ame ( o rd i n ar i l y t h e l e f t a n d r i g h t ch an n e l ) . e a ch s u b f ra me i n cl udes t h e a p pr o p r i a t e 4 - b i t p r e a m b le , u p t o 24 b i ts o f a u dio da ta , a validi ty ( v ) b i t, a user (u) b i t, a c h a n ne l s t a t us (c) b i t, and a n ev en p a r i ty (p) b i t. th e cha n n e l sta t us b i t s a nd t h e us er b i t s acc u m u l a t e o v er ma n y f r a m es t o co n v e y co n t r o l inf o r m a t io n. th e c h anne l s t a t us b i ts acc u m u la t e o v er a 192 f r a m e p e r i o d (cal led a c h a n n e l s t a t us b l o c k). th e us er b i ts acc u m u l a t e o v er 1,176 f r a m es when t h e in ter c o n n e c t is im p l e- m e n t ing the s o -cal led su b c o d e s c h e m e (ei a j cp -2401). th or g a n i z a t i on of t h e ch a n nel s t atu s bl o c k , f r ame s , and su bf r a me s is s h own in t a b l e 9 a nd t a b l e 10 . n o t e tha t t h e ad a v 801 supp or t s t h e pr of e s s i on a l a u d i o st a n d a rd f r om a s o f t w a re p o i n t of v i e w o n ly . t h e d i g i t a l i n te r f a c e supp or t s on ly co n s u m er m o de . ta ble 9. co ns umer a u di o st a nda r d data addre ss 7 6 5 4 3 2 1 0 n channe l sta t u s em pha s i s copy- non- p r o c o right au di o / n = 0 n + 1 ca teg o ry cod e n + 2 channe l nu mber sou r c e nu m b er n + 3 reserve d clock a ccuracy sa m p li ng fr equ e nc y n + 4 re se rved word le ng th n + 5 to (n + 23) reserve d n = 0 x 20 for re c e i v e r channel status b u ffer. n = 0x 38 for tra n s m i t ter c h a n n e l s t a t u s bu ffer.
ADAV801 rev. 0 | page 25 of 56 d a t a b i t s ta ble 10. pro f e s s i ona l a u di o st a nda rd addre ss 7 6 5 4 3 2 1 0 n sa m p l e frequency lock e m p h asis non- au di o pro/ con = 1 n + 1 us e r b i t ma na g e m e n t cha nne l mo de n + 2 ali g n m l e v el us e o f au xi li a r y mo d e en t sou r c e word l e ng th sa m p l e b i ts n + 3 cha nne l id en ti fi c a ti on n + 4 f s sc a l - ing refer e nce s i gnal sa m p l e fre q u e nc y (f s ) res e r v ed digital audio n + 5 reserve d n + 6 a l p h anume r ic channe l o r igin dat a f irst charact e r n + 7 a l p h anume r ic channe l o r igin dat a n + 8 a l p h anume r ic channe l o r igin dat a n + 9 e l o r igin dat a las t charact e r a l p h anume r i c c h a n n n + 1 l p ion dat a first charact e r 0 a h anume r ic channe l de s t inat n + 1 1 a l p h anume r ic channe l de s t inat ion dat a n + 1 2 a l p h anume r ic channe l de s t inat ion dat a n + 1 a l 3 p h anume r ic channe l de s t inat ion dat a last charact e r n + 1 4 local sampl e addres s codel sw n + 1 5 local sampl e addres s code n + 1 6 local sampl e addres s code n + 1 7 local sampl e addres s code m sw n + 1 8 time of day cod e l sw n + 1 9 time of day cod e n + 2 0 time of day cod e n + 2 1 time of day cod e m sw n + 2 2 re l i ab i l it y fl ags re se rved n + 2 3 c y c l i c r e d u n d a n cy c h eck c h aracter (cr c c) n = 0x 20 for re c e ive r channel status b u ffer. a r e o r ga nize d i n to 24 b y tes a nd h a ve t h e in ter p r e t a t i o n s sh own in d t h e n e e d fo r us er in t e r v en t i on. recei v e r s e cti o n the ad a v 801 us es a do u b le-b uf f e r i n g s c h e m e t o ha ndle r e ad- in g cha n nel st a t us a n d us er b i t i n fo r m a t io n. t h e cha n n e l st a t us b i ts a r e a v a i lab l e as a m e m o r y b u f f er , t akin g up 24 co n s e c u t i v e r e g i s t er lo ca t i o n s. th e us er b i ts a r e r e ad usin g an i n dir e c t m e m o r y addr essin g s c h e m e , w h er e t h e r e ce i v e r us er - b i t indir e c t - a ddr ess r e g i ster is p r o g r a mm e d wi t h a n o f fs et to t h e i v er us er b i t da t a r e g i s t er can b e r e ad er r e ad d n = 0x 38 for tra n s m i t ter c h a n n e l s t a t u s bu ffer. the st and a rds a l l o w t h e chan ne l st a t u s bi ts i n e a ch su b f r a me to b e i ndep e n d en t, b u t o r di na r i ly t h e chann e l st a t us b i t i n t h e tw o s u b f ram e s o f e a ch f r a m e a r e t h e s a me . th e chann e l s t a t us b i ts a r e def i ne d dif f er en t l y fo r t h e co n s u m er a u dio st anda r d s and th e p r o f es sio n al a u dio s t anda r d s. th e 192 c h a n n e l s t a t us b i t s t a b l e 9 an d t a ble 10. the s p d i f t r a n smi t t e r an d r e ce i v er ha v e a co m p r e h e n s i v e r e g i s t er s e t. the r e g i s t ers g i v e t h e us er f u l l acce s s t o t h e f u n c t i o n s o f t h e s p dif b l o c k, such as dete c t in g n o n a u d i o a n va lidi ty b i ts, q sub c o d es, p r e a m b les, a nd s o o n . the cha n nel s t a t us b i ts as def i n e d b y t h e iec60958 a nd aes 3 s p ecif ic a t io ns a r e s t o r e d in r e g i s t er b u f f ers fo r e a s e o f us e . an a u t o b u f f er in g f u n c tion al lo ws c h a n n e l sta t us b i ts and us er b i ts r e ad b y th e re c e ive r to b e c o pi e d di re c t ly to t h e t r ans m it te r bl o c k , re mov i ng us er b i t b u f f er , a nd t h e r e c e t o det e r m i n e t h e us er b i ts a t t h a t lo ca t i on. r e adin g t h e r e c e i v us er b i t da t a r e g i s t er a u t o ma t i ca l l y u p da t e s t h e i n dir e c t addr es s r e gi s t e r t o th e n e xt loca ti o n in th e b u f f e r . t y p i call y , th e r e ce i v e r us er b i t i ndir e c t -addr ess r e g i ste r is p r o g r a mm e d to z e r o (t h e s t a r t o f t h e b u f f er), a n d t h e r e ce i v er us er b i t da t a r e g i s t e r i s r e pea t edl y un til all th e b u f f e r s da ta ha s been r e a d . f i gur e 46 a n f i gur e 47 s h o w h o w r e ceivin g t h e c h ann e l s t a t us b i ts and us er b i ts is im ple m e n t e d . 04577-0-026 secondbuffer receive channel status a (24 8 bits) dirin cs buffer (0x20? 0x37) channel status b (24 8 bits) rxcsswitch spdif receive buffer first buffer f i gure 46. channe l status buffer 04577-0-027 buffer spdifin 0...7 8...15 16...23 first 0...7 8...15 16...23 user-bit buffer address = 0x50 address = 0x51 receiver user bit indirect address register receiver user bit data register f i gure 47. r e c e iver user bit b u ffer the s p d i f r e ce i v e b u f f er is u p da t e d co n t in uo usl y b y t h e i n c o m i ng spdi f st re am . o n c e a l l t h e ch a n nel s t a t u s b i t s f b l o c k (192 f o r cha n n e l a and 192 f o r cha n n e l b) a r e r e cei o r t h e v ed , this d t h e bi n t h e c h a n n e l s t a t u s s w it c h bu f f e r re g i s t e r i n e t h e q u i t o b e f er is b y t e s g a n d b e c a u s e t h e c h a n cha n ge , a s o f t war e t , is p r o v ide d t o ti f y th o st co t a t us b i t s i s av a i l a b l e o r s t a t u s f o r m a t i o n h a ve ch ange d f r om a pr e v i ou s bl o c k . t h e f u nc t i on o f th e rxcs b i nt is co n t r o l l ed b y th e rxb c o n f3 b i t in the r e cei v er b u f f er co nf igura t io n r e g i s t er . the si ze o f t h e us er b i t b u f f er ca n b e s e t b y p r o g ra mmin g t h e rxb c o n f0 b i t in t h e r e cei v er b u f f er co nf igura t io n r e g i s t er , as s h own in t a b l e 11. t h e b i ts a r e co p i e d in t o t h e r e ceiv er cha nne l s t a t us b u f f er . b u f f er s t o r es al l 384 b i ts o f c h a n n e l s t a t us inf o r m a t ion, a n r x c s s w i t c h t i deter m es w h e r t h e c h a n nel a o r t h e c h annel b st a t us b i t s a r e r r e d r e ad . th e r e c e i v e cha n ne l s t a t us b i t b u f 2 4 l o n s p a n s t h e addr es s ra n g e f r o m 0x20 t o 0x37. n e l st a t u s bi ts of an s p di f st re am r a rely in t e r r u p t/f l ag b i t, rxcs bi n n o e h n t r o l th a t ei t h e r a n e w b l oc k o f c h a n n e l s t h at t h e f i r s t f i v e b y t e s o f c h a n n e l i n
ADAV801 rev. 0 | page 26 of 56 e r bit bu ffer size tab l e 11. rxb c onf3 fun c tion ality rxbcon f0 receiv e r u s 0 384 bits with preamble z as the start of the block. 1 768 bits with preamble z as the start of the block. the u p da t i ng o f t h e us er b i t b u f f er is co n t r o l l e d b y bi ts rx b c onf 2 C1 a nd bi t 7 to bi t 4 o f t h e cha n nel st a t us r e g i ster , a s s h own in t a b l e 12 a nd t a b l e 13. tab l e 12. rxb c onf2C1 function ality rxbconf bit 2 bit 1 receiv er user bit bu ffer configu r ation 0 0 user bits are ignored. 0 1 update second buffer when first buffer is full. 1 0 format accordi n g to byte 1, bit 4 to bit 7, if pro bit is set. format accordin g to iec60958-3, if p r o bit is clear. tab l e 13. automatic user bit con f iguration bits 7 6 5 4 automatic receiver user bit b u ffer configuration 0 0 0 0 user bits are ignored. 0 1 0 0 aes-18 format: t h e user bit buffer is treated in the same way as when rxbconf 2 C1 = 0b01. 1 0 0 0 user bit buffer is update d in the same way a s when rxbc onf2C1 = 0b01 and rxbconf0 = 0b00. 1 1 0 0 user-defined format: the user bit buffer is treated in the same way as when rx bconf2C1 = 0b01. w h en t h e us er b i t b u f f er has b e en f i l l e d , t h e rx ubi n t in t e r r u p t b i t i n t h e i n t e r r u p t st a t us r e g i st er is s e t, p r o v ide d t h a t t h e rx ubi n t mask b i t is s e t, to in di c a t e t h a t t h e b u f f er has ne w info r m a t io n and can s e w h en t h e u s er da t a is fo r m a t t e d acco r d i n g e and t h e e d i n , e n e l st a t us b u f f er o c c u p i es ts i n g r i n t o th e s p d i f tra n sm i t t e r b u f f e r un til f i ni s h e d lo ading t h e b u f f ers. this fe a t ur e is typ i c a l l y e b e r e ad . f o r t h e s p e c ial c a t o th e iec6095 8-3 s t anda r d in to m e s s a g es made o f inf o r m a t io n uni t s, cal l e d i u s , th e zer o s s t uf f e d b e tween eac h iu an d each m e s s a g e a r e r e m o v e d and o n l y t h e i u s a r e st o r e d . o n ce t h e e nd o f th e m e s s a g e is s e n s e d b y m o re tha t eig h t zer o s betw een i u s, t h e us er b i t b u f f er is u p da te d wi t h t h e co m p lete m e s s a g f i rs t b u f f er b e g i n s lo okin g fo r t h e st a r t o f t h e next m e s s a g e . e a c h iu is st o r e d as a b y t e co n s is tin g o f 1, q , r , s, t , u , v , an d w b i ts (s ee t h e ie c60958-3 s p ec if ica t ion f o r m o r e inf o r m a t io n). w h en 96 i u s a r e r e cei v e d , t h e q s u b c o d e o f t h e iu s is s t o r t h e q sub c o d e b u f f er , co n s is t i n g o f 10 b y t e s. th e q sub c o d e is th e q b i ts ta k e n f r o m ea c h o f th e 96 iu s. th e f i r s t 10 b y t e s (80 b i ts) o f t h e q s u b c o d e con t a i n i n fo r m a t io n s e n t b y cd , m d a nd d a t sys t e m s. th e l a s t 16 b i ts o f th e q subco d e a r e us e d t o p e r f o r m a cr c ch e c k o f t h e q su b c o d e . i f a n er r o r o c c u rs in th e cr c ch eck o f th e q s u bco d e , th e q c r c err o r b i t i s set . this is a st ick y b i t t h a t r e m a in s hig h un t i l t h e reg i st er is r e ad . trans m itter o p er ation the s p d i f t r a n smi t t e r has a si mi la r b u f f er s t r u c t ur e t o t h r e cei v e s e c t ion. the t r a n smi t t e r cha n 24 b y t e s o f t h e r e g i s t er ma p . this b u f f er is lo n g en o u g h t o s t o r e th e 192 b i ts r e q u ir ed f o r o n e c h a nne l o f c h a n nel s t a t us inf o r m a - ti o n . s e t t i n g t h e t x c ssw it c h b i t d e t e rm in e s i f th e d a ta l o a d e d to t h e t r ans m it te r ch a n ne l st a t u s b u f f e r i s i n te nde d f o r c h a n n e l a o r c h a n n e l b . i n m o s t cas e s, th e c h anne l s t a t u s b i fo r c h a n n e l a and c h a n nel b ar e t h e s a me, in w h ich cas e s e t t in g t h e tx_a/b_ s am e b i t r e ads t h e da t a f r o m t h e t r a n s- m i t t e r ch an n e l s t a t u s b u f f e r an d t r ans m i t s i t on b o t h ch an nel s . b e ca us e t h e channel st a t us info r m a t io n is r a r e ly cha n ge d d u r t r a n smissio n , t h e info r m a t io n c o n t a i ne d i n t h e b u f f er is t r a n smi t t e d r e p e a t e d l y . th e dis a b l e_tx_c o p y b i t can b e us e d t o p r e v en t t h e channe l s t a t us b i ts f r o m b e in g co p i e d f r o m t h e tra n sm i t t e r c s b u f f e t h e us e r h a s us e d , if t h e c h anne l a da t a an d c h a n n e l b da t a a r e dif f er en t. s e t t in g t h e b i t pr e v en t s t h e da t a f r o m b e ing co pie d . c l e a r i n g t h b i t allo w s th e da ta t o be co p i e d a n d t h e n tra n sm i t t e d . f i gur e 4 8 s h o w s h o w t h e b u f f ers a r e o r ga ni ze d. 04577-0-028 txcsswitch transmit cs buffer (0x38? 0x4f) channel status a (24 8 bits) channel status b (24 8 bits) ditout spdif transmit buffer f i g u re 48. t r ans m it ter ch ann e l st at us buf f e r a s w i th th e r e c e i v e r s e ct i o n , th e t r a n s m i t t e d u s e r b i t s a r e a l s do ub le- b uf fer e d. this is r e q u ir e d , b e o ca us e , un li k e t h e ch a n n e l e o u t ali g n m e n t t o th e z p r ea m b le . i f i t tin g un til a b i t s a r e 01. b l e 14. t r urations b c o n f 2 - 1 st a t us b i ts, t h e us er b i ts do no t ne cess a r i l y r e p e a t t h e m s e lv es. the us er b i ts c a n b e b u f f er e d i n va r i o u s co nf igura t io n s , as list e d in t a b l e 14. t r an smissio n o f t h e us er b i ts is deter m in e d b y t h s t a t e o f t h e b c o n f3 b i t. i f t h e b i t is 0, t h e us er b i t s b e g i n tra n sm i t ti n g ri gh t a w a y w i t h th i s b i t i s 1, th e use r b i t s d o n o t s t a r t tra n s m z p r ea m b l e occ u r s wh en t h e txb c o n f2C 1 t a a n smitter user bit buffer co nfig t x bit 2 bit 1 transmitter us er bit buffer configuration 0 0 z e r o s a r e t r a n s m i t t e d f o r t h e u s er bits. 0 1 host writes user bits to the buff e r u n t i l i t i s f u l l . 1 0 writes the user bits to the buffer in ius specified by iec60958-3 and tra n smits them according to the standard. 1 1 first 10 bytes of the user-bit buffer are configured to store a q subcode .
ADAV801 rev. 0 | page 27 of 56 table 15. tran smitter user bit buffer size t x b c o n f 0 b u f f e r size 0 384 bits with preamble z as the start of the block. 1 768 bits with preamble z as the start of the block. by usin g st ick y b i ts an d in ter r u p ts, t h e t r an smi t b u f f ers ca n n o ti f y th e h o st o r m i cr oco n tr o l le r wh en t h e f i r s t use r b i t b u f f er has b e en up da t e d an d w h en t h e s e con d t r a n s m i t us er b i t b u f f er is f u l l . th e st icky b i t, txubi n t , is s e t w h e n t h e t r a n smi t us er b i t b u f f er has b e e n u p da te d and t h e s e con d t r an smi t us er b i t b u f f er is r e ad y t o accep t ne w us er b i ts. the s t ick y b i t, txfb int , is s e t w h e n e v er t h e s e co nd t r a n smi t u s er b i t b u f f er is f u l l . an y ne w wr i t es t o t h is b u f f er a r e ig n o r e d un t i l t h e f i rs t t r a n smi t b u f f er is u p da te d . th e s e tw o b i ts a r e lo ca t e d i n t h e i n t e r r u p t st a t us r e g i s t er . w h e n t h e h o s t r e ads t h e in ter r u p t s t a t us r e g i s t er , t h es e b i ts a r e cle a r e d . i n ter r u p ts fo r t h e tx u b in t and tx f b i n t st ick y b i ts can b e ena b le d b y s e tt in g t h e tx ub mask an d t x fbma s k b i ts, r e s p ecti v e l y , in th e i n t e rr u p t s t a t us mask re g i ste r . 04577-0-029 spdif 0 0...7 8...15 16...23 second buffer 0...7 8...15 16...23 user-bit buffer address = 0x52 address = 0x53 transmitter user bit indirect address register transmitter user bit data register f i gure 49. t r ans m it ter u s e r b i t buffer autobuffering the ad a v 801 s p d i f r e cei v er a nd tra n smi t t e r s e c t io n s ha v e an a u to b u f f e r i n g mo d e a l l o w i ng t h e ch a n nel st a t u s and u s e r b i t s to be co p i ed a u t o m a ti call y f r o m th e r e cei v e r t o th e tra n sm i t t e r wi t h o u t us er in ter v en tio n . th e c h a n n e l sta t us and us er b i ts can b e i ndep e n d en t l y s e le c t e d fo r a u t o b u f f er in g usin g t h e a u to _ c sbit s a nd a u to _ u bi t s bit s , re sp e c t i vely , i n t h e a u tob u f f e r r e g i s t er . w h e n t h e r e ce i v er an d t r a n smi t t e r a r e r u nnin g a t t h e s a me s a m p le r a te, t h e t r a n s m i t te d cha n nel st a t us a nd us er b i ts a r e t h e s a me as t h e r e ce i v e d ch annel-st a t us and us er b i ts. i n man y sys t ems, h o w e v e r , i t is l i k e l y tha t t h e r e cei v er an d t r ans m itte r are not r u n n i ng a t t h e s a m e f r e q u e nc y . whe n t h e tra n smi t t e r s a m p le ra t e is hig h er tha n r e cei v er s a m p le ra t e , the c h a n n e l sta t us and us er b i t b l o c k is s o m e tim e s rep e a t ed . th e tra n smi t t e r sa m p le ra t e is lo w e r tha n t h e r e cei v er sa m p le te, t h e cha n nel st a t us an d us er b i t b l o c ks mig h t b e dr o p p e d . e ca us e t h e f i rs t f i v e b y t e s o f t h e cha n n e l s t a t us a r e typ i cal l y co n s t a n t , t h e y c a n b e r e p e a t e d o r dr o p p e d w i t h n o i n fo r m a t ion los s . h o w e v e r , i f th e pr o b i t in th e c h a n n e l sta t us i s se t a n d t h e lo ca l s a m p le ad dr ess co de and t i me-o f- d a y co d e b y tes co n t a i n 9 5 8 -3 s e n t or re p e a t i n g me ss age s . b e c a u s e z e ro - s tu f f i n g s e ss a g es t o b e s u b t rac t e d , t h e zer o s ra ct ed a s w e ll . th e z e r o _ s t u f f _ i u b i t i n t h e y . r u p t. a ch in t e r r u p t in t h e in t e r r u p t st a t us r e g i st er h a s a n ass o c i a t e d mask bi t i n t h e i n te r r u p t st a t u s mask re g i ste r . t h e i n te r r u p t mask b i t m u st b e s e t fo r t h e co r r esp o ndin g in t e r r u p t t o b e g e n e r a t e d . this fe a t ur e al lo ws t h e us er t o de t e r m i n e w h ich f u n c tio n s sh o u ld b e r e s p on de d t o . the d u al f u n c tio n p i n zer o l / int can b e s e t to in dic a t e t h e p r es en c e o f n o a u dio da t a on t h e lef t cha n n e l o r t h e p r es e n c e o f a n i n t e r r u p t s e t in t h e i n t e r r u p t st a t us r e g i st er . a s sh o w n i n t a b l e 16, th e fun c ti o n o f th i s p i n i s se lect ed b y th e in tr pt b i t in d a c c o n t r o l reg i st er 4. table 16. ze r o l/int pin functionality intrpt pin functionali t y w h en r a b info r m a t io n, t h es e b y t e s mig h t b e r e p e a t e d o r d r o p p e d , i n w h ich cas e infor m a t io n c a n b e lost. i t is u p t o t h e us er t o de te r m i n e how to h a nd l e t h i s c a s e . w h en t h e us er b i ts a r e tra n smi t t e d acco r d in g to th e i e c 6 0 fo r m a t , t h e m e ss a g es co n t a i n e d in t h e us er b i ts ca n s t i l l b e w i t h out d r oppi ng is a l lo w e d b e twe e n i u s and m e ss a g es, z e r o s can b e add e d o r s u b t rac t e d t o p r es er v e t h e m e s s a g es. w h en t h e t r a n smi t t e r s a m p l e r a te i s g r e a te r t h a n t h e r e cei v er s a m p le ra t e , ext r a zer o s a r e s t uf f e d bet w ee n t h e m e s s a g es . w h en t h e sa m p l e ra t e o f th e tra n sm i t t e r i s les s th a n t h e sa m p le ra t e o f th e r e ce i v e r , th e z e r o s t uf fe d b e t w e e n t h e m e s s a g e s a r e s u b t rac t e d . i f t h er e a r e n o t e n t h e m en o u g h zer o s b e tw e bet w een iu s a r e s u b t a u t o b u f f er r e g i s t er ena b les t h e addin g o r sub t rac t in g o f zer o s bet w een m e s s a g e s . interrupts the ad a v 801 p r o v ides in t e r r u p t b i ts t o indic a t e the p r es en ce o f cer t a i n con d i t io n s t h a t r e q u ire a t t e n t io n. re a d in g t h e i n te r r upt st a t u s re g i ste r a l l o w s t h e u s e r to de te r m i n e i f a n y of th e in t e rr u p t s ha v e been a s se r t e d . th e b i ts o f th e i n t e rr u p t s t a t u s r e gi s t e r r e m a i n h i gh , i f s e t , u n til th e r e gis t e r i s r e a d . t w o b i ts, s r cer r o r a nd rxer r o r , in d i ca t e i n t e r r u p t c o n d i t io n s i n t h e s a m p le ra t e con v er t e r a n d a n sp d i f r e cei v er er r o r , r e s p e c t i v e l b o t h t h e s e con d i t io n s r e q u ir e a r e ad o f t h e a p p r o p r i a t e er r o r r e g i s t er t o det e r m i n e t h e exac t ca us e o f t h e i n t e r e 0 pin functions as a zerol flag pin. 1 pin functions as an interrupt pin. serial d a t a por t s the ad a v 801 co n t a i n s f o ur f l exi b le s e r i al p o r t s (s po r t s) t o t a t r a n s f er to a n d f r o m t h e co de c. a l l fo ur s p or t s a r e indep e n d en t and can b e co nf ig ur e d as ma ster o r sla v e p o r t s. i n s l a v e m o de , t h e xlr c lk and x b clk sig n als a r e in p u ts t o t h e s e r i al p o r t s. i n mas t er m o de , t h e s e r i al p o r t g e nera t e s t h e xlr c lk and x b clk sig n als. th e mas t er clo c k fo r t h e s p o r t c a n b e s e l e c t e d f r om a n u mb e r of s o u r c e s , a s sh ow n i n f i gur e 50. a l lo w d a
ADAV801 rev. 0 | page 28 of 56 04577-0-031 reg 0x76 bits 4?2 dir pll (512 f s ) dir pll (256 f s ) pllint1 pllint2 mclki xin iclk1 iclk2 pll clock reg 0x06 bits 4?3 mclk adc output port olrclk l k o b c osdata reg 0x76 bits 7?5 dir pll (512 f s ) dir pll (256 f s ) pllint1 pllint2 mclki xin iclk1 iclk2 pll clock reg 0x04 bits 4-3 mclk dac input port i l r c l k i b c l k isdata reg 0x77 bits 4?3 reg 0x00 bits 3?2 reg 0x00 bits 1?0 reg 0x00 bits 4?5 reg 0x76 bits 1?0 mclki xin pllint1 pllint2 iclk1 iclk2 dir pll (512 f s ) dir pll (256 f s ) reg 0x00 bits 1-0 mclki xin pllint1 pllint2 divider divider divider src mclk f i gure 50. sport clock i ng s c he me l e , m c lki in p u t to en s u r e tha t t h e c an d s e r i al p o r t a r e syn c hr o n ize d . the s p o r t s c a n b e s e t i v e da ta in i 2 s, lef t - j u st if ie d o r r i g h t- j u st if ie d fo r m a t s wi t h d i f f er en t w o r d len g t h s b y p r og ra mmin g t h e a p p r o p r i a t e b i ts i n t h e pl a y b a ck r e g i s t er , a u x i l i ar y i n put p o r t re g i ste r , re c o rd re g i ste r , a n d a u x i l i ar y o u t p ut p o r t -con t r ol r e g i ster . f i gur e 51 is a t i ming di ag r a m o f t h e s e ri a l d a ta po rt f o r m a t s . clocking s c heme the ad a v 801 p r o v ides a f l exib le c h o i ce o f o n -c hi p and o f f- chi p cl o c k i ng s o u r c e s . the on-c hi p o s c i l l a tor w i t h d u a l pl l s is i n te nde d to of fe r c o m p l e te s y ste m cl o c k i ng re qu i r e m e n t s for us e wi t h a v a i la ble mpeg e n co d e rs, de co ders, o r a com b ina t io n of c o d e c s . t h e o s c i l l ator f u nc t i o n i s d e s i g n e d f o r ge ne r a t i o n of a 27 mh z vid e o clo c k f r o m a 27 mh z cr y s t a l conn e c t e d b e twe e n t h e xin and x o ut pin s . c a p a ci to rs m u st a l s o b e co n n e c te d b e tw e e n t h es e pin s an d d g nd , as sh o w n in f i g u r e 35. th e ca p a c i t o r val u es s h o u ld b e s p e c i f ie d b y t h e cr ys t a l ma n u fac t ur er . a s q u a r e wa ve versio n o f th e cr ys tal c l o c k is o u t p u t on t h e mclk o p i n. i f t h e sys t em has a 27 mh z clo c k a v a i lab l e , t h is clo c k can b e conn e c te d dir e c t ly to t h e xin pin. c a re shou l d b e t a k e n to e n su re t h a t t h e cl o c k r a te is a p p r op r i a t e f o r wh a t ev e r b l oc k i s co nn ec t e d t o th e se ri al p o r t . f o r e x a m p if th e ad c is r u nnin g f r o m t h e m c lki in p u t a t 256 f s , t h e n t h e mas t er clo c k fo r t h e s p o r t sh o u ld als o r u n f r o m t h e ad t o tra n smi t o r r e c e 04577-0-030 lrcl k bclk sdata lrcl k bclk sdata lrcl k bclk sdata lsb lsb lsb lsb lsb lsb left channel right channel right channel left channel left channel right channel msb msb msb msb msb msb right-justified mode ? select number of bits per channel i 2 s mode ? 16 bits to 24 bits per channel left-justified mode ? 16 bits to 24 bits per channel f i gure 51. s e ri al d a ta mod e s
ADAV801 rev. 0 | page 29 of 56 p u t/o u t p u t s w i t c h in g/ le s in cl ude t h e o u t p u t p o r t s (b o t h 3 - wir e dig i t a l) a nd t h e . dat a p a th the ad a v 801 fea t ur es a dig i tal in m u l t i p le xi n g ma tri x th a t gi v e s f l e x i b ili t y t o th e ra n g e o f pos s i b in p u t an d o u t p ut co n n e c t i o n s. dig i t a l in pu t p o r t s in cl ude p l ay b a c k a n d au x i l i a r y i n p u t ( b o t h 3 - w i r e d i g i t a l ) , a n d s / p d i f (sin g l e- wir e t o t h e on-chi p r e ceiv er). o u t p u t p o r t r e co r d a nd a u x i lia r y s/p d if p o r t (sin g l e-wir e f r o m th e on-c hi p tran smi t t e r). i n te r n a l ly , t h e di r and di t are i n te r f a c e d v i a 3 - w i re i n te r f a c e s the da t a p a t h for e a ch in p u t and o u tp u t p o r t is s e le c t e d b y p r og ra mmin g da t a p a t h c o n t rol reg i st ers 1 and 2. f i gur e 52 s h o w s t h e in t e r n al da t a p a t h s t r u c t ur e o f th e ad a v 801. 04577-0-032 pll adc dac oscillator reference aux data output dit src control registers playback data input dir aux data input record data output f i g u re 52. d a t a p a t h
ADAV801 rev. 0 | page 30 of 56 ad a v 801 h a s a d c a ted co n t r o o r t t o al lo w acces s t o a v 801. e a c h o f th e in t e r n al g h t b i t s w s r e s e r v e d th ese b i ts s h o u l a c e o n t r o l o f th e ad a v 8 . l p o r t i s y c l e o f d a ta tra n sf e r c s . f i gur e 53 s h o w s t h e r m a t o f a n s p i wr i t e th e tran sf er o f a t a is ini t i a t e d o n t h e a t c h . the d a t a r es en t e d on t h e f i rs t s en ts t h e r e g i st er ri t e b i t . f d a t a a r e l o a d ed t o t h p r o v i d ed . i f th i s b i t i s h , a r e ad o p e r a t io n i s i ndic a te d . th e c o n t e n t s o f t h e r e g i s t er es s a r e clo c k e d o u n o n t h e fol l o w in g eig h t c lk s. f o r a r e ad o p e ts a f t e r t h e r e ad/ w r i t e bl o c k e a d s a n the ad a v 801 p r o v ides the us er wi t h the a b ili t y t o wr i t e t o o r r e ad f r o m a b l o c k o f r e g i st ers i n on e co n t in uous o p era t io n. i n s p i m o de , t h e c l a t ch line sho u ld be he ld lo w f o r lo n g er tha n t h e 16 c c lk p e r i o d s t o us e t h e b l o c k r e ad/ w r i te m o de . f o r a wr i t e op era t io n, o n ce t h e ls b has b e en clo c k e d in t o t h e ad a v 801 on t h e 16t h ccl k , th e r e g i st er addr es s as s p ec if ied b y t h e f i rs t s e v e n b i ts o f t h e wr i t e o p era t io n is i n cr e m en t e d and t h e n e xt eig h t b i ts a r e clo c k e d in t o t h e n e xt r e g i st er addr es s. the r e ad op era t io n is simi la r . on ce t h e ls b o f a r e ad r e g i s t er o p era t ion has b e en clo c k e d o u t, t h e r e g i st er addr es s is in cr e m e n te d and t h e da t a f r o m t h e n e x t r e g i ster is clo c k e d o u t on t h e f o l l ow i n g e i g h t c c l k s . f i g u re 5 5 an d fi g u re 5 6 show t h e t i min g dia g ra ms fo r t h e b l o c k wr i t e an d r e ad o p era t io ns. interf ace control the e d i l p th e in t e r n al r e g i s t ers o f th e a d r e g i s t e r s i s e i i de . w h ere b i ts a r e des c r i b e d a (res), d b e p r ogra mm e d as zer o . spi interf c 0 1 i s via a n s p i - com p a t ib le s e r i al p o r t t h e spi c o n t r o a 4 - w i re s e r i a l c o n t ro l p o r t w i t h o n e c o n s i s ti n g o f 16 b i t f o / r e ad o f t h e ad a v 801. d f a l l in g e d ge o f c l p e v e n c c lks r e p r es a d d r e s s r e a d / w i f th i s b i t i s lo w , th e f o llo w in g e i g h t b i t s o e r e gi s t er a d d r e s s hig addr t on t h e c o u t p i c r a t io n, t h e da t a b i b i t s are i g nore d. r d writes clatch cclk cin d0 d8 d0 d14 d9 d8 cout d15 d9 04577-0-033 spi s e ri a l p o r t tim i ng d i ag r a m f i gure 53. 1 4 1 3 1 2 1 1 1 0 987 6543 210 r/w 15 address [6:0] data [7:0] 04577-0-036 r e 54. spi c o r m register data register + 1 data register + 2 data f i g u o n t rol w o r d f at 04577-0-034 register r/w = 0 8 bits clatch cin 8 bits 8 bits 8 bits f i g u re 55. spi bl ock w r ite o p er at i o n register data register + 1 data register + 2 data 04577-0-035 register r/w = 1 8 bits 8 bits 8 bits 8 bits c l a t c h cin don?t care c f i g u re 56. spi bl ock r e ad o p er at io n o u t
ADAV801 rev. 0 | page 31 of 56 r iv1 iv0 div1 table 17. src and clock control registe srcd srcd clk2 clk2div0 cl k1div1 clk1div0 mclksel1 mclksel0 7 6 5 4 3 2 1 0 address = 0000000 (0x00) srcdiv1C0 divides the src master clock. 00 = src master clock is no t divided. vided by 1.5. is divided by 2. is divided by 3. e by 1.5. ck 1 (iclk1). 01 = divide by 1.5. 10 = divide by 2. selection e src m = internal c k 1. ernal clock 2. 6 f s ). 01 = src master clock is di 10 = src master clock 11= src master clock clk2div1C0 clock divider for internal clock 2 (iclk2). 00 = divide by 1. 01 = divid 10 = divide by 2. 11 = divide by 3. clk1div1C0 clock divider for internal clo 00 = divide by 1. 11 = divide by 3. mclksel1C0 clock for th aster clock. 00 loc 01 = int 10 = pll recovered clock (512 f s ). 11 = pll recovered clock (25 table 18. spdif loop res res res res res txmux back control register res res 7 6 5 4 3 2 1 0 address = 0000011 (0x03) txmux selects the so urce for spdif output (ditout). 0 = spdif tran smitter, normal mode. 1 = dirin, loo pback mode. table 19. playback port control register clksrc0 spmode2 spmode1 spmode0 res res res clksrc1 7 6 5 4 3 2 1 0 a ddress = 0000100 (0x04) clksrc1C0 selects the clock source for gene rating the ilrclk and ibclk. 00 = input port is a slave. 01 = recovered pll clock. 10 = internal clock 1. 11 = internal clock 2. spmode2C0 selects the serial format of the playback port. 000 = left-justified. 001 = i 2 s. 100 = 24-bit, right-justified. 101 = 20-bit, right-justified. 110 = 18-bit, right-justified. 111 = 16-bit, right-justified.
ADAV801 rev. 0 | page 32 of 56 2 table 20. auxiliary input port register res res res clksrc1 clksrc0 spmode spmode1 spmode0 7 6 5 4 3 2 1 0 address = 0000101 (0x05) clksrc1C0 selects the clock source for genera ting the iauxlrclk and iauxbclk. 00 = input port is a slave. 01 = recovered pll cock. 10 = internal clock 1. 11 = internal clock 2. spmode2C 0 ut port. tified. right-justified. right-justified. ustified. selects the serial format of auxiliary inp 000 = left-jus 001 = i 2 s. 100 = 24-bit, 101 = 20-bit, 110 = 18-bit, right-justified. 111 = 16-bit, right-j table 21. record por res res clksrc1 clksrc0 wl en1 wlen0 spmode1 spmode0 t control register 7 6 5 4 3 2 1 0 address = 0000110 (0x06) clksrc1C0 selects the cl ock source for gen rclk and obclk. erating the ol 00 = record port is a slave. covered pll clock. lock 2. l output word length. record port. 01 = i 2 s. 10 = reserved. 11 = right-justified. 01 = re 10 = internal clock 1. 11 = internal c wlen1C0 selects the seria 00 = 24 bits. 01 = 20 bits. 10 = 18 bits. 11 = 16 bits. spmode1C0 selects the serial format of the 00 = left-justified.
ADAV801 rev. 0 | page 33 of 56 res c1 cl 1 0 spmo mode0 table 22. auxiliary output port register res clksr ksrc0 wl en wlen de1 sp 7 6 5 4 3 2 1 0 address = 0000111 (0x07) clksrc1C0 clk. selects the clock source for genera ting the oauxlrclk and oauxb 00 = auxiliary record port is a slave. 01 = recovered pl l clock. ecord port. 10 = internal clock 1. 11 = internal clock 2. wlen1C0 selects the serial output word length. 00 = 24 bits. 01 = 20 bits. 10 = 18 bits. 11 = 16 bits. spmode1C0 selects the serial format of the auxiliary r 00 = left-justified. 01 = i 2 s. 10 = reserved. 11 = right-justified. table 23. group dela grpdly6C0 y and mute register mute_src 7 6, 5, 4, 3, 2, 1, 0 address = 0001000 (0x08) m ute_src soft-mutes the output of the sample rate converter. 0 = no mute. y to the sample rate converter fir filter by grpdly6 C 0 inpu ples. 00000 = no de . 1 = 1 sample delay. 1 = soft-mute. grpdly6C0 adds dela t sam 00 lay 000000 0000010 = 2 sample delay. 1111110 = 126 sample delay. 1111111 = 127 sample delay.
ADAV801 rev. 0 | page 34 of 56 ock rxclk1C au table 24. receiver configuration 1 register nocl 0 to_ deemph err1C0 lock 1C0 7 6, 5 4 3, 2 1, 0 address = 0001001 (0x09) noclock selects the source of the receiver clock when the pll is not locked. clock. ph ata from the rece iver based on the channel status information. should take, if the receiver detects a parity or biphase error. ock1C0 tion the receiver should take, if the pll loses lock. 11 = soft-mute of the last valid audio sample. 0 = recovered pll clock is used. 1 = iclk1 is used. rxclk1C0 determines the oversampling ratio of the recovered receiver clock. 00 = rxclk is a 128 f s recovered clock. 01 = rxclk is a 256 f s recovered clock. 10 = rxclk is a 512 f s recovered 11 = reserved. auto_deem automatically de-emphasizes the d 0 = automatic de-emphasis is disabled. 1 = automatic de-emphasis is enabled. err1C0 defines what action the receiver 00 = no action is taken. 01 = last valid sample is held. 10 = invalid sample is replaced with zeros. 11 = reserved. l defines what ac 00 = no action is taken. 01 = last valid sample is held. 10 = zeros are sent out after the last valid sample. table 25. receiv er co ration 2 register sp_pl sp_pll_ sel re s res no nonaudio no_validity nfigu rxmute l 1C0 7 6 5, 4 3 2 1 0 address = 0 001010 (0x0a) rxmute hard-mutes the audio output for the aes 3/spdif receiver. 0 = aes3/spdif receiver is not muted. 1 = aes3/spdif receiver is muted. sp_pll aes3/spdif receiver pll accepts a left/rig ht clock from on e of the four serial ports as the pll reference clock. es3/sp dif preambles is the reference clock to the pll. ports is the reference clock to the pll. re ference clock to the pll when sp_pll is set. nonaudio er is not al lowed into the sample rate converter efined by th e iec61937 standard, then the data from receiver is not allowed into th e src regardless of the state of this bit. the src. s not allo wed into the src, if the nonaudio bit is set. the aes 3/spdif receiver is not allowed into the src. 0 = aes3/spdif receiver data is sent to the src. 1 = data from the aes3/spdif receiver is not allo wed into the src, if the validity bit is set. 0 = left/right clock generated from the a 1 = left/right clock from one of the seri al sp_pll_sel1C0 selects one of the four serial ports as the 00 = playback port is selected. 01 = auxiliary input port is selected. 10 = record port is selected. 11 = auxiliary output port is selected. no when the nonaudio bit is set, data from the aes3/spdif receiv naudio data is due to dts, aac, and so on, as d (src). if the no the aes3/spdif 0 = aes3/spdif receiver data is sent t o 1 = data from the aes3/spdif receiver i no_validity when the validity bit is set, data from
ADAV801 rev. 0 | page 35 of 56 res f5 rxbconf4 nf3 rxb rxbconf0 table 26. receiver buffer configuration register res rxbcon rx bco conf2C1 7 6 5 4 3 2, 1 0 address = 0001011 (0x0b) rxbconf5 if the user bits are formatted accord ing to the iec60958-3 standard and the dat category is dete cted, the user bit enabled only when there is a change in the start (id) bit. interrupt is 0 = user bi t interrupt is enabled in normal mode. if the dat category is detected, the user bit interrupt is enabled only if there is a change in the start (id) bit. termines whether channel a and channel b user bits are stored in the buffer together or separated and b. eceiver channel status is read, which is 192 audio frames. of the receiver channel status block changes from the previous channel iec60958-3 standard. xbconf0 defines the user bit buffer size, if rxbconf2C1 = 01. rt of the buffer. a 1 = rxbconf4 this bit de between a 0 = user bits are stored together. 1 = user bits are stored separately. rxbconf3 defines the function of rxcsbint. 0 = rxcsbint are set when a new block of r 1 = rxcsbint is set only if the first five bytes status block. rxbconf2C1 defines the user bit buffer. e ignored. 00 = user bits ar 01 = updates the second user bit buffer when the first user bit buffer is full. 10 = formats the received user bits accordin g to byte 1, bit 4 to bit 7, of the cha nnel status, if the pro bit is set. if the pro bit is not set, formats the user bi ts according to the 11 = reserved. r 0 = 384 bits with preamble z as the sta 8 b h pr st 1 = 76 its wit eamble z as the rt of the buffer. table 27. transmitter contr ol register res txvalidity txratio2C0 txclksel1C0 txenable 7 6 5, 4, 3 2, 1 0 address = 0001100 (0x0c) txvalidity this bit is used t o set or clear the vali dity bit in the aes3/spdif transmit stream. 0 = audio is suitable for d/a conversion. 1 = audio is not suitable for d/a conversion. txratio2C0 determines the aes3/spdif transmitter to aes3/spd if receiver ratio. 00 = internal clock 1 is the cl 01 = internal clock 2 is the cl ock source for the transmitter. ce for the transmitter. 3/spdif transmitter is disabled. 000 = transmitter to receiver ratio is 1:1. 001 = transmitter to receiver ratio is 1:2. 010 = transmitter to receiver ratio is 1:4. 101 = transmitter to receiver ratio is 2:1. 110 = transmitter to receiver ratio is 4:1. txclksel1C0 selects the clock source for the aes3/spdif transmitter. ock source for the transmitter. 10 = recovered pll clock is the clock sour 11 = reserved. txenable enables the aes3/spdif transmitter. 0 = aes 1 = aes3/spdif transmitter is enabled.
ADAV801 rev. 0 | page 36 of 56 txbconf3 txbconf2C1 txbconf0 table 28. transmitter buffer configuration register iu_zeros3C0 7, 6, 5, 4 3 2, 1 0 address = 0001101 (0x0d) iu_zeros3C0 determines the number of zeros to be stuffed between ius in a message up to a maximum of 8. 0000 = 0. 11 = 7. 8. ser bits. size is configured according to txbconf0. ter user bits when txbconf2 C1 is 01. s with preamble z as the start of the buffer. 0001 = 1. 01 1000 = txbconf3 transmitter user bits can be stored in separate buffers or stored together. 0 = user bits are stored together. 1 = user bits are stored separately. txbconf2C1 configures the transmitter user bit buffer. 00 = zeros are transmitted for the u 01 = transmitter user bit buffer 10 = user bits are written to the transmit bu ffer in ius specified by the iec60958-3 standard. 11 = reserved. txbconf0 determines the buffer size of the tr ansmit 0 = 384 bits with preamble z as the start of the buffer. 1 = 768 bit table 29. channel status switch buffer and transmitter disable_tx_copy res res txcsswitch rxcsswitch res res tx_a/b_same 7 6 5 4 3 2 1 0 a ddress = 0001110 (0x0e) tx_a/b_same transmitter channel status a and b a re the same. the tran smitter reads only from the channel status a buffer and s the data into t place he channel status b buffer. 0 = channel status for a and b are separate. nnel status for a and b are the same. nsmitter channel status buffer to the spdif transmitter 0 = copying transmitter channel status is enabled. tus is disabled. channel status buffer. itter channel sta tus a buffer can be accessed at address locations 0x38 through 0x4f. yte transmitter channel status b buffer can be accessed at address locations 0x38 through 0x4f. 0 = 24-byte receiver channel status a buffer can be accessed at address locations 0x20 through 0x37. 1 = 24-byte receiver channel status b buffer can be accessed at address locations 0x20 through 0x37. 1 = cha disable_tx_copy disables the copying of the channel status bits from the tra buffer. 1 = copying transmitter channel sta txcsswitch toggle switch for the trans mit 0 = 24-byte transm 1 = 24-b rxcsswitch toggle switch for the receive channel status buffer. tab le 30. transmitte t significant byte r message zeros m ros7C0 os msbze 7, 6, 5, 4, 3, 2, 1, 0 address = 0 001111 (0x0f) msbzeros7C0 most significant byte of the number of zeros to be stuffed between iec60958-3 messages (packets). default = 0x00.
ADAV801 rev. 0 | page 37 of 56 icant byte table 31. transmitter message zeros least signif lsbzeros7C0 7, 6, 5, 4, 3, 2, 1, 0 address = 0010000 (0x10) lsbzeros7C0 least significant byte of the number of zeros to be s tuffed between iec60958-3 messages (packets). default = 0x 09. able 32. autobuffer register stuff_iu auto_ubits auto_csbits iu_zeros3C0 t res zero_ 7 6 5 4 3, 2, 1, 0 address = 0010001 (0x11) zero_stuff_iu enables the addition or subtract ion of zeros between ius du ring autobuffering of the user bits in iec60958-3 format. 0 = no zeros added or subtracted. 1 = zeros can be added or subtracted between ius. enables the user bits to be autobuffered auto_ubits be tween the aes3/spdif receiver and transmitter. 0 = user bits are not autobuffered. 1 = user bits are autobuffered. ts to be autobuffere d between the aes3/spdif receiver and transmitter. s are not autobuffered. bits are autobuffered. maximum number of zero-stuffi ng to be added between ius while a utobuffering up to a maximum of 8. 0111 = 7. auto_csbits enables the channel status bi 0 = channel status bit 1 = channel status iu_zeros3C0 sets the 0000 = 0. 0001 = 1. 1000 = 8. 33. sample rat r ad srcratio14Csrcratio08 table e ratio msb egister (re only) res 7 6, 5, 4, 3, 2, 1, 0 address = 0010010 (0x12) srcratio14C0 8 seven most significant bits of the15-bit sample rate ratio. table 34. sam ple rate ratio l sb register (read only) srcratio07Csrcratio00 7, 6, 5, 4, 3, 2, 1, 0 address = 0 010011 (0x13) srcratio07C00 eight least significant bits of the15-bit sample rate ratio. table 35. pream ble-c pre_c15Cpre_c08 msb register (read only) 7, 6, 5, 4, 3, 2, 1, 0 address = 0010100 (0x14) p re_c15C08 eight most significant bits of the 16- bit preamble-c, when nonaudio data is detected according to the iec60937 standard; otherwise, bits show zeros.
ADAV801 rev. 0 | page 38 of 56 d only) pre_c07Cpre_c00 table 36. preamble-c lsb register (rea 7, 6, 5, 4, 3, 2, 1, 0 address = 0010101 (0x 15) pre_c07C00 eight least signif nt bits of th -bit preamb -c, wh en nonaudio data is detect ed according to the iec60937 d; otherwise, bits show zeros. ica e 16 le standar table 37. preamble-d m pr sb register (read only) e_d15Cpre_d08 7, 6, 5, 4, 3, 2, 1, 0 address = 0010110 (0x 16) pre_d15C08 ei nonaudio data is detected according to the iec60937 st nonaudio is used, this becomes the eight most significant bits of ght most significant bits of the 16- bit preamble-d, when andard; otherwise, bits show zeros. when subframe the 16-bit preamble-c of channel b. table 38. preamble-d lsb register (read only) pre_d07Cpre_ d00 7, 6, 5, 4, 3, 2, 1, 0 address = 0010111 (0x 17) pre_d07C0 0 ei mble-d, wh en nonaudio data is detect ed according to the iec60937 standard; otherwise, bits becomes the eight most significant bits of ght least significant bits of the 16-bit prea show zeros. when subframe nonaudio is used, this the 16-bit preamble-c of channel b. table 39. receiver err o rx amble crcerror nostream biphase/ parity lock r register (read only) validity emphasis nonaudio pre nonaudio 7 3 2 1 0 6 5 4 address = 0011000 (0x 18) rxvalidit y th ived stream. is is the validity bit in the aes3 rece e mphasis this bit is set, if the audio data is pre-emphasized. once it has been read, it remains high and does not generate an interrupt unless it changes state. onaudio) is set. once it has b een read, it does not generate another upt unle data bec audio or pe of no ha naudio is bit is set, e audio da s nonaudio due to the det ion of a pream . the nonau preamble type register s what type of preamble was detected. once read, it remains in its state and does not generate an interrupt ster nonaudio this bit is set, when channel status bi t 1 (n interr ss the omes the ty naudio data c nges. no preamble indicate th if th ta i ect b le dio unless it changes state. this bit is the error flag for the channe l status crcerror check. this bit does not clear until the receiver error regi crcerror is read. this bit is set, if there is no aes3/ spdif stream present at the aes3/spdif re ceiver. once read, it remains high and nostream does not generate an interrupt unless it changes state. this bit is set, if a biphase or parity error occurred in the aes3/spdif stream. this bit is not cleared until the register is biphase/parity read. this bit is set, if the pll has locked or cleared when the pll loses lock. once read , it remains in its state and does not generate an interrupt unless it changes state. lock
ADAV801 rev. 0 | page 39 of 56 rxvalid emphasis mask naudio mask ona preamble mask crcerror mask stream mask biphas parity mask lock mask table 40. receiver error mask register mask ity no n udio no e/ 7 6 5 4 3 2 1 0 address = 0 011001 (0x19) rxvalidit y mask rating an interrupt. masks the rxvalidity bit from gene 0 = rxvalidity bit does not generate an interr upt. terrupt. k an interrupt. 0 = nonaudio bit does no t generate an interrupt. 1 = nonaudio bit generates an interrupt. naudio preamble bit from generating an interrupt. 0 = nonaudio preamble bit do es not gene e an interru onaudio preamble bit generates an interrupt. ask nostream mask biphase/parity mask an interrupt. 1 = rxvalidity bit generates an interrupt. emphasis mask masks the emphasis bit from generating an in 0 = emphasis bit does no t generate an interrupt. 1 = emphasis bit generates an interrupt. nonaudio mas masks the nonaudio bit from generating nonaudio preamble masks the no mask rat pt. 1 = n crcerror m masks the crcerror bit from generating an interrupt. 0 = crcerror bit does not generate an interrupt. 1 = crcerror bit generates an interrupt. masks the nostream bit from generating an interrupt. 0 = nostream bit does not generate an interrupt. 1 = nostream bit generates an interrupt. masks the biphase/parity bit fr om generating 0 = biphase/parity bit does not generate an interrupt. 1 = biphase/parity bit generates an interrupt. lock mask masks the lock bit from generating an interrupt. 0 = lock bit does not generate an interrupt. 1 = lock bit generates an interrupt. table 41. sample rate co res res res res too_slow ovrl ovrr mute_ind nverter error register (read only) 7 6 5 4 3 2 1 0 address = 0011010 (0x1a) too_slow this bit is set, when the clock to th e src is too slow, that is, there are no t enough clock cycles to complete the internal convolution. ovrl this bit is set, when the left output data of the sample ra te converter has gone over the full-scale range and has been clipped. this bit is not cleare d until the register is read. ovrr this bit is set, when the ri ght output data of the sample rate converter has gone over the full-scale range and has been clipped. this bit is not cl eared until the register is read. mute_ind mute indicated. this bit is se t, when the src is in fast mode and clicks or pops can be heard in the src output data. the output of the src can be muted, if required, until the sr c is in slow mode. once read, this bit remains in its state and does not generate an interrupt until it has changed state.
ADAV801 rev. 0 | page 40 of 56 sk register res res res res ovrl mask sk e_ table 42. sample rate converter error ma res ovrr ma mut ind mask 7 6 3 2 0 5 4 1 address = 0011011 (0x1b) ovrl mask masks t he ovrl from generating an interrupt. 0 = ovrl bit does not generate an interrupt. 1 = ovrl bit generates an interrupt. ovrr mask masks the ovrr from generating an inte rrupt. ask interrupt. 0 = ovrr bit does not generate an interrupt. 1 = ovrr bit generates an interrupt. reserved. mute_ind m masks the mute_ind from generating an 0 = mute_ind bit does not generate an interrupt. 1 = mute_ind bit generates an interrupt. tab le 43. interrupt st txcsint rxcsdiff rxubint rxcsbint rxerror atus register srcerror txcstint txubint 7 6 5 4 3 2 1 0 address = 0011100 (0x1c) srcerror this bit is set, if one of the sample rate co nverter interrupts is asserted, an d the host should immediately read the gh until the interrupt status register is read. sample rate converter error register. this bit remain s hi txcstint this bit is set, if a write to the tran smitter channel status buffer was made whil e transmitter channel status bits were fer to the spdif transmit buffer. his bit remains high until the interrupt status register is read. it buffer has transmitted its block of channel status. this bit remains ceiver channel status b clock. this bit remains high until read, but do es not generate an interrupt. eiver user bit buffer has a new block or message. this bit remains high until the interrupt rxcsbin it is set, if block of c tus is rea o 0, or if the s when bconf3 = 1. is bit remains gh unti l the interrupt status register is read. is set, if one of the aes3/spdif receiver interru pts is asserted, and the host should immediately read the ins high until the interrupt status register is read. being copied from the transmitter cs buf txubint this bit is set, if the spdif transmit bu ffer is empty. t txcsint this bit is set, if the transmitter cha nnel status b high until the interrupt status register is read. this bit is set, if the receiver channe l status a block is different from the re rxcsdiff rxubint this bit is set, if the rec status register is read. t this b a new hannel sta d wh en rxbc nf3 = channel status ha changed rx th hi rxerror this bit receiver error register. this bit rema
ADAV801 rev. 0 | page 41 of 56 xcstint sk txubint mask txcsbint mask res rxubint mask rxcsbint mask rxerror mask table 44. interrupt status mask register srcerror t mask ma 7 6 5 4 3 2 1 0 address = 0 011101 (0x1d) srcerror mask masks the srcerror bit from generating an interrupt. 0 = srcerror bit does not generate an interrupt. an interrupt. k int bit from generating an interrupt. oes not generate an interrupt. n interrupt. ask 1 = txubint bit generates an interrupt. rrupt. rrupt. nterrupt. t bit from generating an interrupt. bint bit does no t generate an interrupt. xcsbint mask masks the rxcsbint bit from generating an interrupt. nerate an interrupt. nterrupt. rating an interrupt. s not generate an interrupt. rror bit generates an interrupt. 1 = srcerror bit generates txcstint mas masks the txcst 0 = txcstint bit d 1 = txcstint bit generates a txubint m masks the txubint bit from generating an interrupt. 0 = txubint bit does no t generate an interrupt. txcsbint mask masks the txcsbint bit from generating an inte 0 = txcsbint bit does not generate an inte 1 = txcsbint bit generates an i rxubint mask masks the rxubin 0 = rxu 1 = rxubint bit generates an interrupt. r 0 = rxcsbint bit does not ge 1 = rxcsbint bit generates an i masks the rxerror bit from gene rxerror mask 0 = rxerror bit doe 1 = rxe able 45. mute and de-emphasis register res res src_deem1C0 res t res res txmute 7 6 5 4 3 2, 1 0 address = 0011110 (0x1e) txmute mutes the aes3 /spdif transmitter. 0 = transmitter is not muted. 1 = transmitter is muted. s rc_deem1C0 selects the de-emphasis filter for the in put data to the samp le rate converter. mphasis. khz de-emphasis. 00 = no de-emphasis. 01 = 32 khz de-emphasis. 10 = 44.1 khz de-e 11 = 48 table 46. nonaudio preambl res dts-cd preamble nonaudio frame nonaudio subframe_a nonaudio subframe_b e type register (read only) res res res 7 6 5 4 3 2 1 0 address = 0011111 (0x1f) dts-cd preamble this bit is set, if the dts-cd preamble is detected. nonaudio fra me dio me_a subframe nonaudio data onaudio subframe_b this bit is set, if the data received through channel b of the aes3/spdif receiver is subframe nonaudio data according to smpte337m. this bit is set, if the data receiv ed through the aes3/spdif receiver is nonaudio data acco rding to the iec61937 standard or nonaudio data according to smpte337m. nonau subfra this bit is set, if the data receiv ed through channel a of the aes3/spdif receiver is according to smpte337m. n
ADAV801 rev. 0 | page 42 of 56 tatus buffer rcs sb0 table 47. receiver channel s b7Crc 7, 6, 5, 4, 3, 2, 1, 0 addr ess 000 to 01 (0x20 to = 0100 10111 0x37) rcsb7C0 the 24-byte receiver channel status buffer. the pro b d at ad tion 0 this bu d only if the channel status is not autob betwee ceiver an mitter. it is stor e dress loca x20, bit 0. ffer is rea u ffered n the re d trans table 48. t ter ch tus bu tcs b0 ransmit annel sta ffer b7Ctcs 7, 6, 5, 4, 3, 2, 1, 0 addr ess to 10 38 to = 0111000 01111 (0x 0x4f) tcsb7C0 the 24-byte transmi el stat the pr tored a location 0x38, bit 0. this buffer is disa autob etwee iver and transmitter is tter chann us bu ffer. o bit is s t address bled when uffering b n the rece enabled. table 49. receiver user bit buffer indire ess regi rxubaddr07Crxubaddr00 ct addr ster 7, 6, 5, 4, 3, 2, 1, 0 address = 1010000 (0x50) rxub addr07C00 ng to th ss lo ca he rece r bit bu indirect addres s pointi e addre tion in t iver use ffer. table 50 . receiver us 07Crxubdata00 er bit buffer data register rxubdata 7, 6, 5, 4, 3 , 2, 1, 0 address = 1010001 (0x51) rxub data07C00 egister reads eight bi ts of user data from the receiver us er bit buffer pointed to by rxubaddr07C ering of the user bits is enabled; otherw ise, it is a read-only buffer. a read from this r 00. this buffer can be written to when autobuff table 51. transmitte indirect address register baddr00 r user bit buffer txubaddr07Ctxu 7, 6, 5, 4, 3, 2 , 1, 0 address = 1010010 (0x52) txub addr07C00 ress pointing to the address location in the transmitter user bit buffer. indirect add tab le 52. transmitter user bit buffer data00 data register 07Ctxub txubdata 7, 6, 5, 4, 3, 2, 1, 0 a ddress = 1010011 (0x53) txubdata07C00 a write to this register writes eight bi ts of user data to the tr ansmit user bit buffer poi nted to by txubaddr07C00. when user bit autobuffering is en abled, this buffer is disabled. table 53. q subcode crcerror status register (read-only) res res res res res res qcrcerror qsub 7 6 5 4 3 2 1 0 address = 1010100 (0x54) qcrcerror this bit is set, if the crc check of the q subcode fails. th is bit remains high, but does no t generate an interrupt. this bit is cleared once the register is read. qsub this bit is set, if a q subcode has been read into the q subcode buffer (see table 54).
ADAV801 rev. 0 | page 43 of 56 s bit 7 it 6 bit 5 bit 4 bit 3 bit 2 bit bi table 54. q subcode buffer addres b 1 t 0 0x 55 address address address ss control control control control addre 0x56 track tra number ck track track number track number track number track number track number number number 0x57 index index index index index index index index 0x 58 minute te min ute minute minute mi nute minute minute minu 0x59 second second second second second second second second 0x5a frame frame frame frame frame frame frame frame 0x5b zero zero zero zero zero zero zero zero 0x5c absolute minute minute absolute minute absolute minute absolute minute absolute minute absolute minute absolute absolute minute 0x5d absolute second te absolute second absolute second absolute second absolute second absolute second absolute second absolu second 0x5e absolute frame absolute frame absolute frame absolute frame absolute frame absolute frame absolute frame absolute frame table 55. datapath control registe r 1 src1 src0 rec2 rec1 rec0 auxo2 auxo1 auxo0 7 6 5 4 3 2 1 0 address = 1100010 (0x62) src1C0 datapath source select for sam ple rate converter (src). 00 = adc. 01 = dir. 10 = playback. 11 = auxiliary in. rec2C0 datapath sou rce select for record output port. . auxiliary output port. 000 = adc. 001 = dir. 010 = playback. 011 = auxiliary in 100 = src. auxo2C0 datapath source select for 000 = adc. 001 = dir. 010 = playback. 011 = auxiliary in. 100 = src.
ADAV801 rev. 0 | page 44 of 56 r 2 dac0 dit2 dit1 dit0 table 56. datapath control registe res res dac2 dac1 7 6 5 4 3 2 1 0 address = 1100011 (0x63) dac2C0 datapath source sel ect for dac. 00 = adc. 01 = dir. 10 = playback. 11 = auxiliary i n. it. 100 = src. dit2C0 datapath source select for d 000 = adc. 001 = dir. 010 = playback. 011 = auxiliary in. 100 = src. t able 57. dac contr dr_dig chsel1 chse l0 pol1 pol0 muter mutel ol register 1 dr_all 7 6 5 4 3 2 1 0 address = 1100100 (0x64) dr_all ha rd reset a wer-down nd po . 0 = normal, output pins go to v ref level. d reset and low power, output pins go to agnd. except registers. l, left-right. ght. right-left. polarity. 00 = both positive. tive. = right ne ht channel. 1 = har dr_dig dac digital reset. 0 = normal. 1 = reset all chsel1C0 dac channel select. 00 = norma 01 = both ri 10 = both left. 11 = swapped, pol1C0 dac channel 01 = left nega 10 gative. 11 = both negative. muter mute rig 0 = normal. 1 = mute. mutel mute left channel. 0 = normal. 1 = mute.
ADAV801 rev. 0 | page 45 of 56 table 58. dac control register 2 res res dmclk1 dmclk0 dfs1 dfs0 deem1 deem0 7 6 5 4 3 2 1 0 address = 1100101 (0x65) dmclk1C0 dac mclk divider. 00 = mclk. 01 = mclk/1.5. 10 = mclk/2. 11 = mclk/3. elect. clk ). = 4 (mclk 128 f s ). (mclk = 64 f s ). eem1C0 elect. 10 = 32 khz. 11 = 48 khz. dfs1C0 dac interpolator s 00 = 8 (m = 256 f s 01 = 10 = 2 11 = reserved. d dac de-emphasis s 00 = none. 01 = 44.1 khz. t able 59. dac contr register 3 res res res res zfvol zfdata zfpol ol res 7 4 3 2 1 0 6 5 address = 1100110 (0x66) zfv ol dac zero flag on mute and zero volume. 0 1 = disabled. disable. 0 = enabled. 1 = disabled. lag polarity. 0 1 = enabled. zfdata dac zero flag on zero data zfpol dac zero f = active high. = active low. t able 60. dac contr res intrpt zerosel1 zerosel0 res res res res ol register 4 7 6 5 4 3 2 1 0 address = 1100111 (0x67) intrpt this bit selects th unctionality the zerol/ pin. e f of int 0 = pin fun ctions as a zerol flag pin. 1 in. t li ty of the zeror pin when the zerol/ int pin is used as an interrupt. 00 = pin functions as a zeror flag pin. 01 = pin functions as a zerol flag pin. 1 hen either the left or right channel is zero. 1 right channels are zero. = pin functions as an interrupt p zerosel1C0 hese bits control the functiona 0 = pin is asserted w 1 = pin is asserted when both the left and
ADAV801 rev. 0 | page 46 of 56 ll7 5 4 3 2 1 0 table 61. dac left volume register dvo dvoll6 dvoll dvoll dvoll dvoll dvoll dvoll 7 6 5 4 3 2 1 0 address = 1101000 (0x68) dvoll7C 0 . dac left channel volume control 1111111 = 0 dbfs. 1111110 = ?0.375 dbfs. 0000 = ?95.625 dbfs. 000 table 62. dac right volume register lr7 dvolr6 dvolr5 dvolr4 dvolr3 dvolr2 dvolr1 dvolr0 dvo 7 6 5 4 3 2 1 0 a ddress = 1101001 (0x69) dvolr7C0 dac right cha nnel volume control. 11111 11 = 0 d bfs. 1111110 = ?0.375 dbfs. 0000000 = ?95.625 dbfs. table 63. dac left p dlp5 dlp4 dlp3 dlp2 dlp1 dlp0 eak volume register res res 7 6 5 4 3 2 1 0 address = 1101010 (0x6a) dlp5C0 dac left channel p eak volume detection. 000000 = 0 dbfs. 000001 = ?1 dbfs. . 111111 = ?63 dbfs table 64. dac right peak volum e register drp5 drp4 drp3 drp2 drp1 drp0 res res 7 6 5 4 3 2 1 0 address = 1101011 (0x6b) drp5C0 dac right ch annel peak volume detection. 000000 = 0 dbfs. 000001 = ?1 dbfs. 111111 = ?6 3 dbfs. table 65. adc left chan ter agl5 agl4 agl3 agl2 agl1 agl0 nel pga gain regis res res 7 6 5 4 3 2 1 0 address = 1101100 (0x6c) a gl5C0 pga left channel gain control. 000000 = 0 db. 000001 = 0.5 db. 101111 = 23.5 db. 110000 = 24 db. 111111 = 24 db.
ADAV801 rev. 0 | page 47 of 56 gain register table 66. adc right channel pga res res agr5 agr4 agr3 agr2 agr1 agr0 7 6 5 4 3 2 1 0 address = 1101101 (0x6d) agr5C0 pga right channel gain control. 000000 = 0 d b. 000001 = 0.5 db. 101111 = 23.5 db. 110000 = 24 db. 111111 = 24 db. table 67. adc control register 1 amc hp f pw rdwn an a_pd mu ter mu tel pl pd pr pd 7 6 5 4 3 2 1 0 address = 1101110 (0x6e) amc adc modulator clock. 0 = adc mclk/2 (128 f s ). 1 = adc mclk/4 (64 f s ). h pf 1 = hpf enabled. ow wer-down. uter ormal. po er-dow ht power-down. high-pass filter enable. 0 = normal. pwrdwn adc power-down. l. 0 = norma 1 = power-d n. ion po ana_pd adc analog sect 0 = normal. 1 = power-down. m mute adc right channel. 0 = normal. 1 = muted. mutel mute adc left channel. 0 = normal. 1 = muted. plpd pga left power-down. 0 = n 1 = w prpd pga rig n. 0 = normal. 1 = power-down.
ADAV801 rev. 0 | page 48 of 56 r b table 68. adc control register 2 res res es uf_pd res res mcd1 mcd0 7 6 5 4 3 2 1 0 address = 1101111 (0x6f) buf_pd reference buffer power-down control. 0 = normal. n. mcd1C0 ck divider. 3. y 1. 1 = power-dow adc master clo 00 = divide by 1. 01 = divide by 2. 10 = divide by 11 = divide b table 69. adc left v er avoll6 avoll5 avoll4 avoll3 avoll2 avoll1 avoll0 olume regist avoll7 7 6 5 4 3 2 1 0 address = 1110000 (0x70) avo ll7C0 olume control. adc left channel v 1111111 = 1.0 (0 db fs). 996 (?0.00348 dbfs). dbfs). 0039 (?48.18 dbfs). 1111110 = 0. 1000000 = 0.5 (?6 0111111 = 0.496 (?6.09 dbfs). 0000000 = 0. table 70. a dc right avolr6 avolr5 avolr4 avolr3 avolr2 avolr1 avolr0 volume register avolr7 7 6 5 4 3 2 1 0 address = 1110001 (0x71) avolr7C0 adc rig ht chan me co nel volu ntrol. 11 111 1 = 1.0 bfs). 0 = 0.996 (?0.00348 dbfs). 96 (?6.09 dbfs). ). 1 111111 (0 d 1000000 = 0.5 (?6 dbfs). 0111111 = 0.4 0000000 = 0.0039 (?48.18 dbfs table 71. adc left p gister 5 alp4 alp3 alp2 alp1 alp0 eak volume re res res alp 7 6 5 4 3 2 1 0 address = 1110010 (0x72) alp5C0 adc left channel peak volume detectio n. 000000 = 0 db fs. bfs. 000001 = ?1 d 111111 = ?63 dbfs. table 72. adc right egister res arp5 arp4 arp3 arp2 arp1 arp0 peak volume r res 7 6 5 4 3 2 1 0 addr ess = 1110011 (0x73) arp5C0 adc right channel pea k volume detection. 000000 = 0 dbfs. 000001 = ?1 dbfs. 111111 = ?63 dbfs.
ADAV801 rev. 0 | page 49 of 56 lk1 lk0 div table 73. pll control register 1 dirin_c dirin_c mclko p lldiv pll2pd pll1pd xtlpd sysclk3 7 6 5 4 3 2 1 0 address = 1110100 (0x74) dirin_clk 1-0 nt to sysclk3. recovered spdif clock se 00 = sysclk 3 comes from pll block. . the recovered spdif clock from dirin. clkodiv generate mclko. . y 2 to generate the pll master clock. . ll2. own. n xtal oscillator. down. for sysclk3. 01 = reserved 10 = reserved. 11 = sysclk3 is m divide input mclk by 2 to 0 = disabled. 1 = enabled plldiv divide xin b 0 = disabled. 1 = enabled pll2pd power-down p 0 = normal. 1 = power-down. pll1pd power-down pll1. 0 = normal. 1 = power-d xtlpd power-dow 0 = normal. 1 = power- sysclk3 clock output 0 = 512 f s . 1 = 256 f s . t able 74. pll control register 2 sel2 doub2 fs1 fs0 sel1 doub1 fs2_1 fs2_0 7 6 5 4 3 2 1 0 address = 1110101 (0x75) fs2_1C0 sa mpl rate se t for pll2. e lec 00 = 48 khz. z. . io select for pll2. ub2 lected samp le rate on pll2. d. select for pll1. rved. . 11 = 44.1 khz. sel1 oversample ratio select for pll1. 0 = 256 f s . 1 = 384 f s . doub1 double-selected samp le rate on pll1. 0 = disabled. 1 = enabled. 01 = reserved. 10 = 32 kh 11 = 44.1 khz sel2 oversample rat 0 = 256 f s . 1 = 384 f s . do double-se 0 = disabled. 1 = enable fs1C0 sample rate 00 = 48 khz. 01 = rese 10 = 32 khz
ADAV801 rev. 0 | page 50 of 56 egister 1 d c ac aclk1 aclk0 i _1 _0 table 75. internal clocking control r dclk2 clk1 d lk0 lk2 clk2 iclk2 7 6 5 4 3 2 1 0 address = 1110110 (0x76) dclk2C0 dac clock source select. 000 = xin . i. lint2. ll (512 f s ). 101 = dir pll (256 f s ). xin. c clock source select. in. 1. r for internal clock iclk2. 001 = mclk 010 = pllint1. 011 = pl 100 = dir p 110 = xin. 111 = aclk2C0 ad 000 = x 001 = mclki. 010 = pllint 011 = pllint2. 100 = dir pll (512 f s ). 101 = dir pll (256 f s ). 110 = xin. 111 = xin. iclk2_1C0 source selecto 00 = xin. 01 = mclki. 10 = pllint1. 11 = pllint2. table 76. internal clo l register 2 res iclk1_1 iclk1_0 pll2int1 pll2int0 pll1int cking contro res res 7 6 5 4 3 2 1 0 address = 1110111 (0x77) iclk1_1C0 source selector for internal clock iclk1. 00 = xin. 01 = mclki. 10 = pllint1. 11 = pllint2. pll2int1C0 pll2 internal selector (see figure 38). 00 = fs2. 01 = fs2/2. 10 = fs3. 11 = fs3/2. pll1int pll1 internal selector. 0 = fs1. 1 = fs1/2.
ADAV801 rev. 0 | page 51 of 56 er ce pll2_source es res res table 77. pll clock source regist pll1_sour res res r res 7 6 5 4 3 2 1 0 address = 1111000 (0x78) pll1_sour ce selects the clock source for pll1. 0 = xin. 1 = mclki. pll2_sou rce ck source for pll2. selects the clo 0 = xin. 1 = mclki. table 78. pll output register res dirinpd dirin_pin res sysclk1 sysclk2 sysclk3 enable res 7 6 5 4 3 2 1 0 address = 1111010 (0x7a) dirinpd this bit powers dow n the spdif receiver. 0 = normal. 1 = power-down. dirin_pin this bit determi nes the input levels of the dirin pin. down to 200 mv according to aes3 requirements. ons section. ysclk1 ysclk2 lk2 output. 0 = enabled. ysclk3 es the sysclk3 ou enabled. bled. 0 = dirin accepts input signals 1 = dirin accepts input signals as defined in the specificati s enables the sysclk1 output. 0 = enabled. 1 = disabled. s enables the sysc 1 = disabled. s enabl tput. 0 = 1 = disa
ADAV801 rev. 0 | page 52 of 56 gaincntr1C0 re cmode1C0 limdet alcen table 79. alc control register 1 fssel1C0 7, 6 5, 4 3, 2 1 0 address = 1111011 (0x7b) fssel1C0 these bits should equal the sample rate of the adc. 00 = 96 khz. 01 = 48 khz. 10 = 32 khz. 11 = reserved. gaincntr1C0 these bits determine the limit of the counter used in limited recovery mode. 00 = 3. 01 = 7. 10 = 15. 11 = 31. recmode1C0 these bits determine which recovery mo de is used by the alc section. 00 = no recovery. 01 = normal recovery. 10 = limited recovery. 11 = reserved. limdet these bits limit detect mode. 0 = alc is used when either channel exceeds the set limit. 1 = alc is used only when both channels exceed the set limit. alcen these bits enable alc. 0 = disable alc. 1 = enable alc. table 80. alc control register 2 res recth1C0 atkth1C0 rectime1C0 atktime 7 6, 5 4, 3 2, 1 0 address = 1111100 (0x7c) recth1C0 recovery threshold. 00 = ?2 db. 01 = ?3 db. 10 = ?4 db. 11 = ?6 db. atkth1C0 attack threshold. 00 = 0 db. 01 = ?1 db. 10 = ?2 db. 11 = ?4 db. rectime1C0 recovery time selection. 00 = 32 ms. 01 = 64 ms. 10 = 128 ms. 11 = 256 ms. atktime attack timer selection. 0 = 1 ms. 1 = 4 ms.
ADAV801 rev. 0 | page 53 of 56 table 81. alc control register 3 alc reset 7, 6, 5, 4, 3, 2, 1, 0 address = 1111101 (0x7d) alc reset a write to this register restarts the alc operation. the value written to this register is irrelevant. a read from this register gives the gain reduction factor.
ADAV801 rev. 0 | page 54 of 56 layout considerations getting the best performance from the ADAV801 requires a careful layout of the printed circuit board (pcb). using separate analog and digital ground planes is recommended, because these give the currents a low resistance path back to the power supplies. the ground planes should be connected in only one place, usually under the ADAV801, to prevent ground loops. the analog and digital supply pins should be decoupled to their respective ground pins with a 10 f to 47 f tantalum capacitor and a 0.1 f ceramic capacitor. these capacitors should be placed as close as possible to the supply pins. adc the adc uses a switch capacitor input stage and is, therefore, particularly sensitive to digital noise. sources of noise, such as plls or clocks, should not be routed close to the adc section. the capxn and capxp pins form a charge reservoir for the switched capacitor section of the adc, so keeping these nodes electrically quiet is a key factor in ensuring good performance. the capacitors connected to these pins should be of good quality, either npo or cog, and should be placed as close as possible to capxn and capxp. dac the dac requires an analog filter to filter out-of-band noise from the analog output. a third-order bessel filter is recommended, although the filter to use depends on the f the application. pll the pll can be used to generate digital clocks, either for use internally or to clock external circuitry. because every clock is a potential source of noise, care should be taken when using the pll. the ADAV801s pll outputs can be enabled or disabled, as required. if the pll clocks are not required by external circuitry, it is recommended that the outputs be disabled. to reduce cross-coupling between clocks, a digital ground trace can be routed on either side of the pll clock signal, if required. the pll has its own power supply pins. to get the best performance from the pll and from the rest of the ADAV801, it is recommended that a separate analog supply be used. where this is not possible, the user must decide whether to connect the pll supply to the analog (av dd ) or digital (dv dd ) supply. connecting the pll supply to av dd gives the best jitter performance, but can degrade the performance of the adc and dac sections slightly due to the increased digital noise created on the av dd by the pll. connecting the pll supply to dv dd keeps digital noise away from the analog supply, but the jitter specifications might be reduced depending on the quality of the digital supply. using the layout recommendations described in this section helps to reduce these effects. reset and power-down considerations when the ADAV801 is held in reset by bringing the reset requirements o pin low, a number of circuit blocks remain powered up. for example, the crystal oscillator circuit based around the xin and xout pins is still active, so that a stable clock source is available when the ADAV801 is taken out of reset. also, the vco associated with the spdif receiver is active so that the receiver locks to the incoming spdif stream in the shortest possible time. where power consumption is a concern, the individual blocks of the ADAV801 can be powered down via the control registers to gain significant power savings. table 82 shows typical power savings when using the power-down bits in the control registers. table 82. typical power requirements operating mode av dd (ma) dv dd (ma) odv dd (ma) dir_v dd (ma) power (mw) normal 50 25 5 5 280.5 reset low 30 4 2.5 1 123.75 power-down bits 12 0.1 1.3 0.7 46.53
ADAV801 rev. 0 | page 55 of 56 outline dimensions top view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc 10.00 bsc sq 1.60 max seating plane 0.75 0.60 0.45 view a 12.00 bsc sq 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3.5 0 0.15 0.05 pin 1 compliant to jedec standards ms-026bcd f i g u re 57. 6 4 -l ead l o w p r of i l e q u ad f l at p a ckag e [l qf p ] (st - 64-2) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature range control interface dac outp uts package descri ption package option ADAV801as t z 1 ?40c to +85c spi single-ended 64-lead low profile quad flat package [lqfp] st-64-2 ADAV801as t z- reel 1 ?40c to +85c spi single-ended 64-lead low profile quad flat package [lqfp] st-64-2 1 z = pb fr ee pa rt .
ADAV801 rev. 0 | page 56 of 56 notes ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04577?0?7/04(0)

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